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参数资料
| 型号： | FOD8320 |
| 厂商： | Fairchild Optoelectronics Group |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | OPTO GATE DRIVE 2.5A 5-SOIC |
| 标准包装： | 2,000 |
| 系列： | OPTOPLANAR® |
| 电压 - 隔离： | 5000Vrms |
| 通道数： | 1，单向 |
| 电流 - 输出 / 通道： | 3A |
| 传输延迟高 - 低 @ 如果： | 285ns @ 7mA ~ 16mA |
| 电流 - DC 正向(If)： | 25mA |
| 输入类型： | DC |
| 输出类型： | 栅极驱动器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-SOIC（0.362"，9.20mm 宽）5 引线 |
| 供应商设备封装： | 5-SOP |
| 包装： | 管件 |
Switching Characteristics
Apply over all recommended conditions, typical value is measured at V DD = 30V, V SS = Ground, T A = 25°C unless
otherwise speci?ed.
Symbol
t PHL
Parameter
Propagation Delay Time to
Logic Low Output (9)
Conditions
I F = 7mA to 16mA, Rg = 10 Ω ,
Cg =10nF, f = 10kHz,
Min.
150
Typ.
285
Max.
400
Units
ns
Figure
10, 11,
12, 13,
Duty Cycle = 50%
14, 27
t PLH
Propagation Delay Time to
Logic High Output (10)
150
260
400
ns
10, 11,
12, 13,
14, 27
PWD
Pulse Width Distortion (11)
25
100
ns
|t PHL – t PLH |
PDD
(Skew)
Propagation Delay Difference
Between Any Two Parts (12)
-250
250
t R
Output Rise Time
60
ns
27
(10% to 90%)
t F
Output Fall Time
60
ns
27
(90% to 10%)
t ULVO ON
t ULVO OFF
ULVO Turn On Delay
ULVO Turn Off Delay
I F = 10mA, V O > 5V
I F = 10mA, V O < 5V
0.8
0.4
μs
μs
|CM H |
|CM L |
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
T A = 25°C, V DD = 30V,
I F = 7 to 16mA, V CM = 2000V (13)
T A = 25°C, V DD = 30V, V F = 0V,
V CM = 2000V (14)
35
35
50
50
kV/μs
kV/μs
28
28
Notes:
9. t PHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the
falling edge of the V O signal.
10. t PLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the
rising edge of the V O signal.
11. PWD is defined as | t PHL – t PLH | for any given device.
12. The difference between t PHL and t PLH between any two FOD8320 parts under same operating conditions, with equal
loads .
13. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of
the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. V O > 15.0V).
14. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of
the common pulse signal, Vcm, to assure that the output will remain low (i.e. V O < 1.0V).
?2010 Fairchild Semiconductor Corporation
FOD8320 Rev. 1.0.6
6
www.fairchildsemi.com
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