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参数资料
| 型号： | FODM8061R2 |
| 厂商： | Fairchild Optoelectronics Group |
| 文件页数： | 4/12页 |
| 文件大小： | 0K |
| 描述： | ISOLATOR 3.3/5V LOGIC OUT 5-MFP |
| 产品目录绘图： | FODM Series 5-MFP |
| 标准包装： | 2,500 |
| 系列： | OPTOPLANAR® |
| 电压 - 隔离： | 3750Vrms |
| 通道数： | 1，单向 |
| 电流 - 输出 / 通道： | 50mA |
| 数据速率： | 10Mbps |
| 传输延迟高 - 低 @ 如果： | 43ns @ 7.5mA |
| 电流 - DC 正向(If)： | 50mA |
| 输入类型： | DC |
| 输出类型： | 开路集电极 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-SMD 模块 |
| 供应商设备封装： | 5-MFP |
| 包装： | 带卷 (TR) |
Electrical Characteristics (Apply over all recommended conditions)
(T A = -40oC to +110oC, 3.0V ≤ V CC ≤ 5.5V), unless otherwise specified.
Typical value is measured at T A = 25oC and V CC = 3.3V.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
INPUT CHARACTERISTICS
V F
BV R
Forward Voltage
Input Reverse Breakdown Voltage
I F = 10mA, Fig. 1
I R = 10μA
1.05
5.0
1.45
1.8
V
V
I FHL
Threshold Input Current
V O = 0.6V, I OL (sinking) = 13mA,
T A < 85oC, Fig. 2
T A = 85oC to 110 oC
3.4
4.2
5.0
7.5
mA
OUTPUT CHARACTERISTICS
V OL
Logic LOW Output Voltage
I F = rated I FHL ,
0.4
0.6
V
I OL (sinking) = 13mA, Fig.3
I OH
I CCL
I CCH
Logic HIGH Output Current
Logic LOW Output Supply Current
Logic HIGH Output Supply Current
I F = 250μA, V O = 3.3V, Fig. 4
I F = 250μA, V O = 5.0V, Fig. 4
I F = 10mA, V CC = 3.3V, Fig. 5, 7
I F = 10mA, V CC = 5.0V, Fig. 5, 7
I F = 0mA, V CC = 3.3V, Fig. 6, 7
I F = 0mA, V CC = 5.0V, Fig. 6, 7
8.0
2.1
6.0
7.5
4.0
6.0
50.0
30.0
8.5
10.0
7.0
9.0
μA
μA
mA
mA
mA
mA
Switching Characteristics (Apply over all recommended conditions)
(T A = -40oC to +110oC, 3.0V ≤ V CC ≤ 5.5V, I F = 7.5mA), unless otherwise specified.
Typical value is measured at T A = 25oC and V CC = 3.3V
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Date Rate
R L = 350 ?
10
Mbps
t PHL
Propagation Delay Time to Logic R L = 350 ? , C L = 15pF,
43
80
ns
Low Output
Fig. 8 and 11
t PLH
Propagation Delay Time to Logic R L = 350 ? , C L = 15pF,
50
80
ns
High Output
Fig. 8 and 11
PWD
Pulse Width Distortion,
R L = 350 ? , C L = 15pF,
7
25
ns
| t PHL - t PLH |
Fig. 9
t PSK
Propagation Delay Skew
R L = 350 ? , C L = 15pF (7)
40
ns
t R
Output Rise Time, (10% to 90%) R L = 350 ? , C L = 15pF,
20
ns
Fig. 10 and 11
t F
Output Fall Time, (90% to 10%)
R L = 350 ? , C L = 15pF,
10
ns
Fig. 10 and 11
|CM H |
|CM L |
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
I F = 0mA, V O > 0.8 x V CC ,
V CM = 1000V (8) , Fig. 12
I F = 7.5mA, V O < 0.8V,
V CM = 1000V (8) , Fig. 12
20
20
40
40
kV/μs
kV/μs
Notes
7. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between any two units
from the same manufacturing date code that are operated at same case temperature (±5°C), at same operating
conditions, with equal loads (R L = 350 ? and C L = 15pF), and with an input rise time less than 5ns.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to
assure that the output will remain low.
?2009 Fairchild Semiconductor Corporation
FODM8061 Rev. 1.0.3
4
www.fairchildsemi.com
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