参数资料
型号: FPF1005
厂商: Fairchild Semiconductor
文件页数: 7/9页
文件大小: 0K
描述: IC LOAD SWITCH P-CH MOSF 6-MLP
标准包装: 1
系列: IntelliMax™
类型: 高端开关
输出数: 1
Rds(开): 70 毫欧
内部开关:
电流限制: 1.5A
输入电压: 1.2 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-MLP
供应商设备封装: 6-MLP(2x2)
包装: 标准包装
产品目录页面: 1217 (CN2011-ZH PDF)
其它名称: FPF1005DKR
Description of Operation
The FPF1005 & FPF1006 are low R DS(ON) P-Channel load
switches with controlled turn-on. The core of each device is a
55m ? P-Channel MOSFET and a controller capable of
functioning over a wide input operating range of 1.2-5.5V. The
ON pin, an active HI TTL compatible input, controls the state of
the switch. The FPF1006 contains a 120 ? on-chip load resistor
for quick output discharge when the switch is turned off.
However, V OUT pin of FPF1006 should not be connected
directly to the battery source due to the discharge mechanism of
the load switch.
Application Information
Typical Application
V IN
V OUT
V IN = 3.3V
-
C IN
OFF ON
ON
FPF1005/6
GND
R L
C OUT
V ON = 3.3V
Input Capacitor
To limit the voltage drop on the input supply caused by transient
in-rush currents when the switch turns-on into a discharged load
capacitor or short-circuit, a capacitor needs to be placed
between V IN and GND. A 1μF ceramic capacitor, C IN , placed
close to the pins is usually sufficient. Higher values of C IN can
be used to further reduce the voltage drop during higher current
application.
Output Capacitor
A 0.1μF capacitor, C OUT , should be placed between V OUT and
GND. This capacitor will prevent parasitic board inductance
from forcing V OUT below GND when the switch turns-off. Due to
the integral body diode in the PMOS switch, a C IN greater than
C OUT is highly recommended. A C OUT greater than C IN can
cause V OUT to exceed V IN when the system supply is removed.
This could result in current flow through the body diode from
V OUT to V IN .
Board Layout
For best performance, all traces should be as short as possible.
To be most effective, the input and output capacitors should be
placed close to the device to minimize the effects that parasitic
trace inductances may have on normal and short-circuit
operation. Using wide traces or large copper planes for all pins
(V IN , V OUT , ON and GND) will help minimize the parasitic
electrical effects along with minimizing the case to ambient
thermal impedance.
FPF1005-FPF1006 Rev. G
7
www.fairchildsemi.com
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