参数资料
| 型号： | FSA321UMX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 4/12页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH MULTIMEDIA 10-UMLP |
| 标准包装： | 5,000 |
| 功能： | 音频，USB 开关 |
| 电路： | 1 x DPDT |
| 导通状态电阻： | 11 欧姆（USB），2.7 欧姆（音频） |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 1.8 V ~ 4.3 V |
| 电流 - 电源： | 500µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-UFQFN |
| 供应商设备封装： | 10-uMLP（1.4x1.8） |
| 包装： | 带卷 (TR) |
Lattice Semiconductor
ispGDX2 Family Data Sheet
9
Table 3. ispGDX2 Supported I/O Standards
The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated
with a bank consistent with their location.
Table 4. I/O Standards Supported by Dedicated Inputs
For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelines.
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-
back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the
sysIO Standard
Nominal VCCO
Nominal VREF
Nominal VTT
LVCMOS 3.3
3.3V
—
LVCMOS 2.5
2.5V
—
LVCMOS 1.8
1.8V
—
LVTTL
3.3V
—
PCI 3.3
3.3V
—
PCI -X
3.3V
—
AGP-1X
3.3V
—
SSTL3 class I & II
3.3V
1.5V
SSTL2 class I & II
2.5V
1.25V
CTT 3.3
3.3V
1.5V
CTT 2.5
2.5V
1.25V
HSTL class I
1.5V
0.75V
HSTL class III
1.5V
0.9V
0.75V
HSTL class IV
1.5V
0.9V
1.5V
GTL+
1.8/2.5/3.3V
1.0V
1.5V
LVPECL
1, 2, 3
3.3V
—
LVDS
2.5/3.3V
—
Bus-LVDS
2.5/3.3V
—
1. LVPECL drivers require three resistor pack (see Figure 17).
2. Depending on the driving LVPECL output specication, GDX2 LVPECL input driver may require terminating resistors.
3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.
LVCMOS
LVDS
All other ASIC I/Os
Global OE Pins
Yes
No
Yes
2
Global MUX Select Pins
Yes
No
Yes
2
Resetb
Yes
No
Yes
2
Global Clock/Clock Enables
Yes
2
ispJTAG Port
Yes
1
No
TOE
Yes
No
1. LVCMOS as dened by the VCCJ pin voltage.
2. No PCI clamp.
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FSA321UMX_F113 | 功能描述:多路器开关 IC Multimedia & USB2 Hi-Speed & Aud Swtch RoHS:否 制造商:Texas Instruments 通道数量:1 开关数量:4 开启电阻（最大值）:7 Ohms 开启时间（最大值）: 关闭时间（最大值）: 传播延迟时间:0.25 ns 工作电源电压:2.3 V to 3.6 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UQFN-16 |
| FSA3230 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:High-Speed USB2.0 / Mobile High- Definition Link (MHLa?￠) with Negative Swing Audio |
| FSA3230UMX | 功能描述:电源开关 IC - USB HiSpeed USB 2.0 MHL w/Neg Swing Audio RoHS:否 制造商:Micrel 电源电压-最小:2.7 V 电源电压-最大:5.5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-8 封装:Tube |
| FSA3259 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Dual SP3T Analog Switch |
| FSA3259BQX | 功能描述:模拟开关 IC FINISHED GOOD RoHS:否 制造商:Texas Instruments 开关数量:2 开关配置:SPDT 开启电阻（最大值）:0.1 Ohms 切换电压（最大）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压:2.7 V to 4.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-16 |
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