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参数资料
| 型号： | FSA8009UMX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC AUDIO JACK DETECTOR/SW 10UMLP |
| 标准包装： | 1 |
| 类型： | 音频插孔探测器，带视频开关 |
| 应用： | MP3 播放器，便携式媒体播放器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-UFQFN |
| 供应商设备封装： | 10-uMLP（1.4x1.8） |
| 包装： | 标准包装 |
| 其它名称： | FSA8009UMXDKR |
6
Precision Edge
SY89534/35L
Micrel, Inc.
M9999-110308
hbwhelp@micrel.com or (408) 955-1690
AC ELECTRICAL CHARACTERISTICS
TA = 0
°CTA = +25°CTA = +85°C
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
fIN
Reference Input Frequency
———
14
—
160
———
MHz
fOUT
Output Frequency Range
———
33.33
—
500
———
MHz
tVCO
Internal VCO Frequency Range
600
—
1000
600
—
1000
600
—
1000
MHz
tskew
Within Device(11)
Within Bank
—
25
50
—
050
—
050
ps
Bank-to-Bank
—
60
150
—
60
150
—
60
150
ps
Part-to-Part Skew(12)
—————
200
——
200
ps
tLOCK
Maximum PLL Lock Time
—————
10
——
10
ms
tJITTER
Cycle-to-Cycle Jitter(13) (Pk-to-Pk)
—————
50
———
ps
Period Jitter(14)
(rms)
——
50
——
50
——
50
ps
tpw (min)
Minimum Pulse Width
———
50
——
50
——
ns
Target PLL Loop Bandwidth
Feedback Divider Ratio: 66(15)
—
1.0
——
1.0
——
1.0
—
MHz
Feedback Divider Ratio: 30(15)
—
2.0
——
2.0
——
2.0
—
MHz
tDC
fOUT Duty Cycle
———
45
50
55
45
50
55
%
tr, tf
Output Rise/Fall Time
ps
(20% to 80%)
LVPECL_Out
——
400
—
250
400
——
400
(SY89535L) LVDS_Out
——
450
—
300
450
——
450
tOUTPUT_RESET
(16)
—————
10
———
ns
tHOLD_FSEL
(16)
———
5
—————
ns
tSETUP_FSEL
(16)
———
5
—————
ns
tOUTPUT_SYNC
(16)
———
1
—————
VCO
clock cycle
FSEL-to-Valid Output Transition Time
————
50
————
ns
All VCC pins = +3.3V ±10%
NOTES:
11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
12. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
13. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn–Tn+1
where T is the time between rising edges of the output signal.
14. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that
signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Parameter guaranteed by
design and characterization.
15. Using recommended loop filter components.
16. See
“Timing Diagrams."
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