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参数资料
| 型号： | FSAR001BNY |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 电源模块 |
| 英文描述： | AC-DC REG PWR SUPPLY MODULE |
| 封装： | GREEN, MS-001BA, DIP-8 |
| 文件页数： | 8/12页 |
| 文件大小： | 494K |
| 代理商： | FSAR001BNY |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSAR001 Rev. 1.0.0
5
FSAR001
—
AC-DC
Linear
Regulator
Electrical Characteristics
VIN=open, VDD=VOUT+1 V, CVDD=470 F/ 25 V, COUT=10 F/ 16 V, IOUT=1 mA, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDD Section
VTH-ON
Turn-on Threshold Voltage
(VOUT=5V)
VDD Pin
9
10
11
V
VTH-OFF
Turn-off Voltage (VOUT=5V)
VDD Pin
3
4
5
V
IDD-ST
Startup Current of VDD Pin
VDD Pin
10
30
A
IDD-OP
Operating Supply Current
IOUT=1mA
1.0
1.5
2.0
mA
VDD-OVP
Threshold of VDD OVP
VOUT+3.0 VOUT+3.5
VOUT+4.0
V
VDD-OVPHYS Threshold of VDD OVP Hysteresis
0.8
1.0
1.2
V
tVDD-OVP
Time Delay of VDD OVP
1.5
s
VIN Section
VVIN
Supply Voltage
600
V
ST Section
IST
Supply Current from ST Pin
VAC=90V (VDC=120V),
VDD=10F
2.50
3.75
5.00
mA
IST-LC
Supply Current After Startup
HV=500V, VDD=VDD-
OFF+1V
1
20
A
DET Section
VDET_MAX
Turn-Off Synchronous Voltage
0.90
0.95
1.00
V
VDET_MAXHYS Turn-Off Synchronous Voltage Hysteresis
0.08
0.10
0.12
V
VDET_MIN
Turn-On Synchronous Voltage
0.08
0.14
0.20
V
VDET_MINHYS Turn-Off Synchronous Voltage Hysteresis
0.08
0.14
0.20
V
IDET
DET Current
0.1
A
VOUT Section
UVPVout
Output Pin Under-Voltage Protection
-10.0
-12.5
-15.0
%
VACC
Output Voltage Accuracy
-2
2
%
LR
Load Regulation
IOUT=1mA to Maximum
-2
2
%
ΔVOUT (VIN) Line Regulation dVOUT/dVIN
-0.2
0.2
%/V
ILIM
Current Limit
VDD=VOUT+3V
110
140
170
mA
VDrop
Dropout Voltage (VOUT=5V)
IOUT=35mA
0.3
0.4
0.5
V
IG
Ground Pin Current
(5)
Output Current =
Maximum Load
1.5
2.0
mA
tDOUT-ST
Output Voltage Rising Time
(VOUT=12V) VDD to VOUT
VOUT=0%~90%
COUT=1F
40
50
60
s
PSRR
Ripple Rejection
(6)
f= 50Hz, COUT=10F,
IOUT =35mA
60
dB
f =100Hz, COUT=10F,
IOUT =35mA
TOTP
Protection Junction Temperature
(6)
150
°C
THYS
Restart Junction Temperature
(6)
TOTP-40
°C
Notes:
5.
For VDrop=1V of VOUT=3.3V version, the test condition is modified to VDD=VOUT+1.5V.
6.
Guaranteed by design.
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