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参数资料
| 型号： | FSDM1265RBWDTU |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC SWIT PWM GREEN CM HV TO220F |
| 标准包装： | 400 |
| 输出隔离： | 隔离 |
| 频率范围： | 60 ~ 72kHz |
| 输入电压： | 8 V ~ 20 V |
| 输出电压： | 650V |
| 功率（瓦特）： | 110W |
| 工作温度： | -50°C ~ 125°C |
| 封装/外壳： | TO-220-6 全封装，成形引线 |
| 供应商设备封装： | TO-220F-6L（成形） |
| 包装： | 管件 |
| 产品目录页面： | 1222 (CN2011-ZH PDF) |
FSDM1265RB
Functional Description
1. Star-tup: In previous generations of Fairchild Power
Switches (FPS TM ), the Vcc pin had an external start-up to
the DC input voltage line. In the newer switches, the startup
resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(C vcc ) that is connected to the Vcc pin as illustrated in
Figure 4. When the Vcc pin reaches 12V, the FSDM1265RB
begins switching and the internal high voltage current source
is disabled. Then, the FSDM1265RB continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless Vcc goes below the
stop voltage of 8V.
V DC
C Vcc
2.1 Pulse-by-pulse current limit : Because current mode
control is employed, the peak current through the Sense-FET
is limited by the inverting input of PWM comparator (Vfb*)
as shown in Figure 5. Assuming that the 0.9mA current
source flows only through the internal resistor (2.5R +R= 2.8
k ? ), the cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (Vfb) exceeds 2.5V,
the maximum voltage of the cathode of D2 is clamped at this
voltage, thus clamping Vfb*. Therefore, the peak value of
the current through the Sense FET is limited.
2.2 Leading edge blanking (LEB): When the internal Sense
FET is turned on, usually the reverse recovery of the
primary-side capacitance and the secondary-side rectifier
causes a high current spike through the SenseFET. causes
Excessive voltage across the Rsense resistor can lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FSDM1265RB employs a
leading edge blanking (LEB) circuit. This circuit inhibits the
PWM comparator for a short time (T LEB ) after the
SenseFET is turned on.
3
Vcc
I start
6
Vstr
Vcc
I delay
Vref
I FB
8V/12V
Vcc good
Vref
Vo
Vfb
H11A817A
C B
4
D1
D2
2.5R
OSC
SenseFET
+
Gate
Internal
Bias
Figure 4. Internal startup circuit
KA431
V SD
V fb *
-
R
OLP
driver
R sense
Figure 5. Pulse width modulation (PWM) circuit
3. Protection Circuit: The FSDM1265RB has several self
2. Feedback Control: FSDM1265RB employs current mode
control, as shown in Figure 5. An opto-coupler (such as the
H11A817A) and shunt regulator (such as the KA431) are
typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resisto r in addition to the offset voltage makes it possible
to control the switching duty cycle. When the reference pin voltage
of the KA431 exceeds the internal reference voltage of 2.5V, the
H11A817A LED current increases, thereby pulling down the
feedback voltage and reducing the duty cycle. Typically this
h appens when the input voltage is increased or the output
load is decreased.
protective functions such as overload protection (OLP), over
voltage protection (OVP) and thermal shutdown (TSD). Because
these protection circuits are fully integrated into the IC without
external components, the reliability can be improved without
increasing cost. Once the fault condition occurs, switching is
terminated and the SenseFET remains off. This causes Vcc to fall.
When Vcc reaches the UVLO stop voltage (8V), the protection is
reset and the internal high voltage current source charges the Vcc
capacitor via the Vstr pin. When the Vcc reaches the UVLO start
voltage (12 V), the FSDM1265RB resumes its normal operation.
Thus, the auto-restart alternately enables and disables the switching
of the power SenseFET until the fault condition is eliminated
(see Figure 6).
11
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