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| 型号： | FSH310410-1M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 4100 MHz, QCC16 |
| 封装： | ROHS COMPLIANT PACKAGE-16 |
| 文件页数： | 1/7页 |
| 文件大小： | 512K |
| 代理商： | FSH310410-1M |
INTELLIGENT INTERACTIVE SYNTHESIZER
SURFACE MOUNT MODEL: FSH310410-1M
3100 - 4100 MHz
OPTIMIZED LOOP PARAMETER
This product is manufactured under one or more of the following patents. Approved: 5,160,810; 5,122,621; 5,390,349; 5,416,449; 5,650,754; 5,805,431; 6,525,623; 6,850,575;
7,088,189; 7,180,381; 7,196,591; 7,262,670; 7,265,642; 7,292,113; 7,365,612; 7,495,525; 2,548,311; 2,548,317; 7,545,229; 7,580,693; 7,586,381; 7,605,670; 7,636,021; 2,533,623
| Pending: 60/493075; 60/501371 & 60/501790; 60/527957 & 60/528670; 60/563481; 60/564173; 60/589090; 60/601823; 60/605791; EV31369834; 11/259766; 60/622485 &
60/710310; 10/937525/60/736901; 60/732787; 7,495,525; 2,548,311; 2,548,317; 7,545,229; 2,563,174; 7,580,693; 7,612,296; 2,524,751
Copyright Synergy Microwave Corporation
201 McLean Boulevard Paterson, New Jersey 07504 USA Tel: (973) 881-8800 Fax: (973) 881-8361
E-Mail: sales@synergymwave.com World Wide Web: http://www.synergymwave.com
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FEATURES:
Exceptionally Low Phase Noise
Optimized Reference Sidebands
Lead Free - RoHS Compliant
Patented REL-PRO Technology
Small Size, Surface Mount
Buffered Output
Phase Noise
-150
-140
-130
-120
-110
-100
-90
-80
-70
100
1000
10000
100000
1000000
10000000
Offset Frequency (Hz)
Ph
as
eN
ois
e(
dBc
/H
z)
3100 MHz
3600 MHz
4100 MHz
SPECIFICATIONS (Rev. B 12/20/10)
Frequency
3100 - 4100 MHz
Step Size
10 MHz
Reference Input Frequency
10 MHz 1
Reference Input Voltage
1.0 V p-p to 3.3 V p-p
Bias Voltage
Vcc
V (Vdc)
I (mA Max.)
Digital
+5
15
VCO
+5
65
Tune
+12
10
Lock Detect Indicator
CMOS 3.3 V
Output Power
+5 dBm (Min.)
Spurious Suppression
75 dB (Typ.)
Harmonic Suppression
20 dB (Typ.)
Settling Time
6 mSec (Typ.) 2
Output Impedance
50 Ohms (Nom.)
Typical Phase Noise
Offset
Phase Noise
@ 10 kHz
-92 dbc/Hz
@ 100 kHz
-98 dbc/Hz
Operating Temperature Range -40 to +85 °C
Programming
See Application Note: AN7100
1
Reference input frequency is programmable (See AN7100) in multiples of the step
size, 10 MHz is the default setting. 150 MHz (Max.)
2
From the rising edge of LE to stable lock detect
Absolute Maximum Ratings
Storage Temp. Range
-55 to +125 C
Bias Voltage (Digital)
+5.25 V
Bias Voltage (Tune)
+16 V
Bias Voltage (VCO)
+5.5 V
DC Voltage Applied to RF Out
±25 V
Package #
273LF
PORT CONFIguRATION
Pin 1 - Reset **
Pin 2,3 - NC
Pin 4 - Error flag
Pin 5 - Latch Enable In
Pin 6 - Ref. In
Pin 7 - Vcc (Digital)
Pin 8 - Vcc (Tune)
Pin 9 - Vcc (VCO)
Pin 13 - RF Out
Pin 14 - Lock Detect Out *
Pin 15 - Data In
Pin 16 - Clock In
All Others - Ground
NC - No Connection
* High when locked (source/sink 500 uA)
** A low on this input will reset the internal controller. Leave unconnected for
normal operation.
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