参数资料
型号: FSQ500N
厂商: Fairchild Semiconductor
文件页数: 8/12页
文件大小: 0K
描述: IC PWM/SENSEFET 130KHZ 8-MDIP
标准包装: 50
系列: FPS™
输出隔离: 隔离
频率范围: 120kHz ~ 140kHz
输入电压: 5.5 V ~ 10 V
输出电压: 700V
功率(瓦特): 6.5W
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-DIP
包装: 管件
Functional Description
1. Startup and V CC Regulation : At startup, an internal
high-voltage current source supplies the internal bias
and charges the external capacitor (C A ) connected to
the V CC pins, as illustrated in Figure 15. An internal
high-voltage regulator (HV/REG) located between the
V O
FOD817A
V FB
C B
2
V CC V CC
I DELAY
D1
I FB
D2
8R
OSC
SenseFET
Drain and V CC pins regulates the V CC to 6.5V and
supplies operating current. Therefore, FSQ500N needs
no auxiliary bias winding.
Transformer
KA431
V SD
+
V FB *
-
R
OLP
Gate
driver
R sense
D
C A
V CC
3
6.5V
I CH
I START
HV/REG
2
Figure 16. Pulse Width Modulation (PWM) Circuit
3. Protection Circuits : The FSQ500N has two self-
protective functions: overload protection (OLP) and
thermal shutdown (TSD). While OLP is implemented as
V REF
Figure 15.
UVLO
Startup Block
auto-restart mode, there is no switching when TSD
triggers. Once the overload condition is detected;
switching is terminated, the senseFET remains off, and
HV/REG turns off. This causes V CC to fall. When V CC
falls below the under-voltage lockout (UVLO) stop
voltage of 5.0V, the protection is reset and the startup
2. Feedback Control : FSQ500N employs current-mode
control, as shown in Figure 16. An opto-coupler (such
as the FOD817A) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the R sense resistor makes it possible to
control the switching duty cycle. When the reference pin
voltage of the regulator exceeds the internal reference
voltage of 2.5V, the opto-coupler LED current
increases, pulling down the feedback voltage and
reducing the duty cycle. This typically occurs when the
circuit charges the V CC capacitor. When V CC reaches
the start voltage of 6.0V, the FSQ500N resumes its
normal operation. If the fault condition is still not
removed, the senseFET and HV/REG remain off and
V CC drops to V STOP again. In this manner, the auto-
restart can alternately enable and disable the switching
of the power senseFET until the fault condition is
eliminated, as shown in Figure 17.
Because these protection circuits are fully integrated
into the IC without external components, reliability is
improved without increasing cost.
line input voltage increases or the output load current
decreases.
V DS
Power
on
OLP
occurs
OLP
removed
2.1 Pulse-by-Pulse Current Limit : Because current-
mode control is employed, the peak current through
the senseFET is limited by the non-inverting input of
PWM comparator (V FB *), as shown in Figure 16.
Assuming that 225μA current source flows only
through the internal resistor (8R + R = 12k Ω ), the
cathode voltage of diode D2 is about 2.7V. Since D1
is blocked when the feedback voltage (V FB ) exceeds
2.7V, the maximum voltage of the cathode of D2 is
clamped at this voltage, clamping V FB *. Therefore, the
peak value of the current through the senseFET is
limited.
V CC
6.5V
6.0V
5.0V
t
2.2 Leading-Edge Blanking (LEB) : At the instant the
internal senseFET is turned on, a high-current spike
Normal
operation
Fault
situation
Normal
operation
occurs through the senseFET, caused by primary-
side capacitance and secondary-side rectifier reverse
recovery. Excessive voltage across the R sense resistor
would lead to incorrect feedback operation in the
current mode PWM control. To counter this effect, the
FPS employs a leading-edge blanking (LEB) circuit.
This circuit inhibits the PWM comparator for a short
time (t LEB = 250ns) after the senseFET turns on.
Figure 17.
Auto Restart Protection Waveforms
? 2009 Fairchild Semiconductor Corporation
FSQ500N ? Rev. 1.0.0
8
www.fairchildsemi.com
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