参数资料
型号: FT24C64A-UTG-T
厂商: Fremont Micro Devices USA
文件页数: 6/17页
文件大小: 0K
描述: IC EEPROM 64KBIT 1MHZ 8TSSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 400kHz,1MHz
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 标准包装
其它名称: 1219-1123-6
24C32A, 24C64A
Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18 th clock cycle
signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal,
the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the
micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27 th clock cycle. Another 8-
bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends
an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its
maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read,
the micro-controller can terminate the sequential read by not acknowledging the last data word received, but
sending a STOP bit afterwards instead (figure 6).
(C) RANDOM READ
Random read is a two-steps process. The first step is to initialize the internal address counter with a target read
address using a “dummy write” instruction. The second step is a current address read.
To initialize the internal address counter with a target read address, the micro-controller issues a START bit first,
follows by a valid device address with the read/write bit (8 th ) set to “0”. The EEPROM will then acknowledge.
The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of
sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to
read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and
continue to execute the new instruction - which is to read the current address (figure 7).
Figure 3: Byte Write
S
W
T
R
S
A
R
T
DEVICE
ADDRESS
I
T
E
FIRST WORD
ADDRESS
SECOND WORD
ADDRESS
DATA
T
O
P
SDA LINE
*** #
M
S
B
L R A
S / C
B W K
M
S
B
A
C
K
L A
S C
B K
A
C
K
Figure 4: Page Write
S
W
T
R
S
SDA LINE
A
R
T
M
S
B
DEVICE
ADDRESS
I
T
E
L R A
S / C
B W K
FIRST WORD
ADDRESS(N)
*** #
M
S
B
A
C
K
SECOND WORD
ADDRESS(N)
L A
S C
B K
DATA(N)
A
C
K
...
T
O
DATA(N+X) P
A
C
K
DS3005J-page 6
? 2009 Fremont Micro Devices Inc.
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