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参数资料
| 型号： | FT24C64A-UTR-T |
| 厂商： | Fremont Micro Devices USA |
| 文件页数： | 4/17页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 1MHZ 8TSSOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | 1219-1114-6 |
24C32A, 24C64A
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read
mode, or after completing a self-time internal programming operation.
Figure 1: Timing diagram for START and STOP conditions
SCL
SDA
START
Condition
Data
Valid
Data
Transition
STOP
Condition
Figure 2: Timing diagram for output ACKNOWLEDGE
START Condition
SCL
Data in
Data out
ACK
DEVICE ADDRESSING
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid
read or write command. The first four most significant bits of the device address must be 1010, which is common to all
serial EEPROM devices. The next three bits are device address bits. These three device address bits (5 th , 6 th and 7 th ) are
to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an
ACKNOWLEDGE signal after the 8 th read/write bit, otherwise the chip will go into STANDBY mode. However,
matching may not be needed for some or all device address bits (5 th , 6 th and 7 th ) as noted below. The last or 8th bit is a
read/write command bit. If the 8th bit is at V IH then the chip goes into read mode. If a “0” is detected, the device enters
programming mode.
DS3005J-page 4
? 2009 Fremont Micro Devices Inc.
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