参数资料
型号: FT93C56A-ISR-T
厂商: Fremont Micro Devices USA
文件页数: 5/19页
文件大小: 0K
描述: IC EEPROM 2KBIT 2MHZ 8SOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K(256 x 8 或 128 x 16)
速度: 250kHz,1MHz,2MHz
接口: 3 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOP
包装: 标准包装
其它名称: 1219-1134-6

93C46/A, 93C56/A, 93C66/A
INSTRUCTION SETS DESCRIPTION
(A) READ
The Read (READ) instruction contains the Address code for the memory location to be read. After the
instruction and address are decoded, data from the selected memory location is available at the serial output pin
DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that when
a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
(B) ERASE/WRITE ENABLE
To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is
first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming
instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains
enabled until an Erase/Write Disable (EWDS) instruction is executed or V CC power is removed from the part.
(C) ERASE/WRITE DISABLE
To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all
programming modes and should be executed after all programming operations. The operation of the READ
instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
(D) ERASE
The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The
self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for
another instruction.
(E) WRITE
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location.
The self-timed programming cycle, t WP , starts after the last bit of data is received at serial data input pin DI. The
DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (t CS ). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the
memory location at the specified address has been written with the data pattern contained in the instruction and
the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high
after the end of the self-timed programming cycle, t WP .
(F) ERASE ALL
The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily
used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (t CS ). The ERAL instruction is valid only at V CC = 5.0V ± 10%.
(G) WRITE ALL
The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the
instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low
for a minimum of 250 ns (t CS ). The WRAL instruction is valid only at V CC = 5.0V ± 10%.
? 2007 Fremont Micro Devices Inc.
DS3020D-page 5
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