参数资料
型号: FTLF1424P2WCD
元件分类: 光收发
英文描述: FIBER OPTIC TRANSCEIVER, 1285-1345nm, 4250Mbps(Tx), 4250Mbps(Rx), SURFACE MOUNT, LC CONNECTOR
封装: ROHS COMPLIANT PACKAGE
文件页数: 5/11页
文件大小: 736K
代理商: FTLF1424P2WCD
FTLF1424P2xCR and FTLF1424P2xCD SFP Product Specification – April 2007
F i n i s a r
II.
Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Max
Unit
Ref.
Maximum Supply Voltage
Vcc
-0.5
4.5
V
Storage Temperature
TS
-40
85
°C
Case Operating Temperature
TOP
-10
70
°C
Relative Humidity
RH
0
85
%
1
III.
Electrical Characteristics (TOP = -10 to 70 °C, VCC = 3.00 to 3.60 Volts)
Parameter
Symbol
Min
Typ
Max
Unit
Ref.
Supply Voltage
Vcc
3.00
3.60
V
Supply Current
Icc
200
300
mA
Transmitter
Input differential impedance
Rin
100
Ω
2
Single ended data input swing
Vin,pp
250
1200
mV
Transmit Disable Voltage
VD
Vcc – 1.3
Vcc
V
3
Transmit Enable Voltage
VEN
Vee
Vee+ 0.8
V
Transmit Disable Assert Time
10
us
Receiver
Single ended data output swing
Vout,pp
250
800
mV
4
Data output rise/fall time < 4.25 Gb/s
tr, tf
175
ps
5
Data output rise/fall time = 4.25 Gb/s
tr, tf
120
ps
5
LOS Fault
VLOS fault
Vcc – 0.5
VccHOST
V
6
LOS Normal
VLOS norm
Vee
Vee+0.5
V
6
Power Supply Rejection
PSR
100
mVpp
7
Deterministic Jitter Contribution
< 4.25 Gb/s
RX
Δ DJ
51.7
ps
8
Total Jitter Contribution < 4.25 Gb/s
RX
Δ TJ
122.4
ps
Deterministic Jitter Contribution
= 4.25 Gb/s
RX
Δ DJ
25.9
ps
8
Total Jitter Contribution = 4.25 Gb/s
RX
Δ TJ
61.2
ps
Notes:
1.
Non-condensing.
2.
AC coupled.
3.
Or open circuit.
4.
Into 100 ohm differential termination.
5.
20 – 80 %
6.
LOS is LVTTL. Logic 0 indicates normal operation; logic 1 indicates no signal detected.
7.
All transceiver specifications are compliant with a power supply sinusoidal modulation of 20 Hz to 1.5
MHz up to specified value applied through the power supply filtering network shown on page 23 of the
Small Form-factor Pluggable (SFP) Transceiver MultiSource Agreement (MSA)
1, September 14, 2000.
The Power Supply Rejection applies for a supply voltage range of 3.15 to 3.6 V.
8.
Measured with DJ-free data input signal. In actual application, output DJ will be the sum of input DJ
and
DJ.
Δ
Finisar Corporation April 5, 2007 Rev F1
Page 3
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