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参数资料
| 型号： | FXLA104UMX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 4/18页 |
| 文件大小： | 0K |
| 描述： | TRANSLATOR 4BIT DUAL LV 16UMLP |
| 标准包装： | 1 |
| 逻辑功能： | 变换器，双向，3 态 |
| 位数： | 4 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 数据速率： | 140Mbps |
| 通道数： | 1 |
| 输出/通道数目： | 4 |
| 差分 - 输入:输出： | 无/无 |
| 传输延迟（最大）： | 4ns |
| 电源电压： | 1.1 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-UMLP |
| 供应商设备封装： | 16-UMLP（1.8x2.6） |
| 包装： | 标准包装 |
| 其它名称： | FXLA104UMXDKR |
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLA104 Rev. 1.0.9
12
FXLA104
—
Low-Voltage
Dual-Suppl
y
4-Bit
Voltage
Translator
I/O Architecture Benefit
The FXLA104 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXLA104 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A
B, and a LH transition
occurs on the B port; the FXLA104 internal I/O
architecture automatically changes direction from A
B
to B
A.
During HL / LH transitions, or “Dynamic Mode,” a strong
output driver drives the output channel in parallel with a
weak
output
driver.
After
a
typical
delay
of
approximately 10ns – 50ns, the strong driver is turned
off, leaving the weak driver enabled for holding the logic
state of the channel. This weak driver is called the “bus
hold.” “Static Mode” is when only the bus hold drives the
channel. The bus hold can be over ridden in the event
of a direction change. The strong driver allows the
FXLA104 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where ICC is typically < 5A.
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (IIHOLD) is VCC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(IIODH, IIODL) is VCC dependent and guaranteed in the DC
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
Electrical Characteristics, IOHD, and IOLD.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FXLA104UMX_12 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low-Voltage Dual-Supply 4-Bit Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing |
| FXLA104UMX_F106 | 功能描述:转换 - 电压电平 Config Volt Xlator RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| FXLA108 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low-Voltage Dual-Supply 8-Bit Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing |
| FXLA108_12 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low-Voltage Dual-Supply 8-Bit Voltage Translator with Configurable Voltage Supplies and Signal Levels, 3-State Outputs, and Auto Direction Sensing |
| FXLA108BQX | 功能描述:总线收发器 Dual Supply 8-Bit Voltage Translator RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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