参数资料
型号: FZL4145D
厂商: SIEMENS A G
元件分类: 外设及接口
英文描述: Quad Driver Incl. Short-Circuit Signaling
中文描述: 0.0025 A 4 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDIP18
封装: PLASTIC, DIP-18
文件页数: 3/10页
文件大小: 109K
代理商: FZL4145D
FZL 4145 D
Semiconductor Group
3
Block Diagram
The switching threshold at inputs Dl and ENA can be adjusted between 1.5 V and 7 V
via connection TS:
V
TS
= 0 V;
input threshold = 1.5 V (for 5 V logic)
V
TS
= 0 to 5 V;
input threshold =
V
TS
+ 1.5 V
V
TS
=
V
S
:
input threshold = 7 V (for 12/15 V and 24/28 V logic)
If the output is disabled due to the logic states of inputs Dl or ENA this disable is effective
over the total supply voltage range between
V
S
= 0 V and
V
S
= 35 V.
The inputs are protected with clamp diodes.
DI
ENA
C
Q
TS
W
SQ
GND
Driver inputs
Enable input
Clock capacitor
Outputs
Input for threshold switching
Input for output current limiter
Signaling output
Ground
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