参数资料
型号: GAL22V10D-15LPI
厂商: Lattice Semiconductor Corporation
文件页数: 8/23页
文件大小: 0K
描述: IC SPLD 5V 24-PDIP
标准包装: 300
可编程类型: EE PLD
宏单元数: 10
输入电压: 4.5 V ~ 5.5 V
速度: 15ns
安装类型: 通孔
封装/外壳: 24-DIP(0.300",7.62mm)
供应商设备封装: 24-PDIP
包装: 管件
其它名称: Q6795010U
Specifications GAL22V10
14
(Vref Typical = 3.2V)
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc (min.)
tpr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
twl
tsu
Device Pin
Reset to Logic "0"
Vc c
CL K
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Typical Input
Typical Output
Power-Up Reset
Input/Output Equivalent Schematics
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