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参数资料
| 型号： | GLT441M08-50FA |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Output LDO, 100mA, Fixed(2.85V), Low Noise, Fast Transient Response 8-SOIC |
| 中文描述： | 为512k × 8的CMOS动态RAM的快速页面模式 |
| 文件页数： | 7/16页 |
| 文件大小： | 399K |
| 代理商： | GLT441M08-50FA |
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1
)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
Notes
1.
An initial pause of 200
μ
s is required after power-up followed by any 8 RAS
only Refresh orCAS
before RAS Refresh cycles to initialize the internal circuit.
2.
V
IH(min.)
and V
IL(min.)
are reference levels for measuring timing of input signals. Transition times
are measured between V
IH(min.)
and V
IL(max.)
are assumed to be 5ns for all inputs.
3
. Measured with an equivalent to 1 TTL loads and 50pF.
4.
For read cycles, the access time is defined as follows:
Input Conditions
Access Time
t
RAD
≤
t
RAD(MAX.)
and t
RCD
≤
t
RCD(MAX.)
t
RAC(MAX.)
t
RAD(max.)
< t
RAD
and t
RCD
≤
t
RCD(MAX.)
t
AA(MAX.)
t
RCD(max.)
< t
RCD
t
CACMAX.)
t
RAD(MAX.)
and t
RCD(MAX.)
indicate the points which the access time changes and are not the limits of
operation.
5.
t
WCS
,t
RWD
,t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data sheet
as electric characteristics only. If t
WCS
≥
t
WCS(min.)
, the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle.If t
CWD
≥
t
CWD
(
min.)
,t
RWD
≥
t
RWD
(min.)
and
t
AWD
≥
t
AWD(min.)
, then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6.
t
AR
,t
WCR
, and t
DHR
are referenced to t
RAD(max.)
.
7.
t
OFF(max.)
and t
OEZ(max.)
define the time at which the output achieves the open circuit condition and are
not referenced to V
OH
or V
OL
.
8.
t
CRP(min)
requirement should be applicable for RAS ,
CAS cycle preceded by any cycles.
9.
Either t
RCH(min.)
or t
RRH(min.)
must be satisfied for a read cycle.
10.
t
WP(min.)
is applicable for late write cycle or read modify write cycle. In early write cycles,t
WCH(min.)
should be satisfied.
11.
This specification is referenced to CAS falling edge in early write cycles and to WEfalling edge in
late write or read modify write cycles.
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| GLT441M08-50FB | Single Output LDO, 100mA, Fixed(2.85V), Low Noise, Fast Transient Response 8-SOIC |
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相关代理商/技术参数 |
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|---|---|
| GLT441M08-50FB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT441M08-50FC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT441M08-50J3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT441M08-50J4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT441M08-50P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
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