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| 型号： | GLT5640L32 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Synchronous DRAM 2M x 32 SDRAM |
| 中文描述： | 200万的CMOS同步DRAM × 32内存 |
| 文件页数： | 15/72页 |
| 文件大小： | 2315K |
| 代理商： | GLT5640L32 |
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G-LINK
GLT5640AL16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.0.1)
G-Link Technology Corporation, Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw
TEL : 886-2-27968078
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3.Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damaged or
malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is in idle state and ready for normal operation.
4.Programming the Mode Register
The mode register is programmed by the mode register set command using address bits BA0,BA1,A11 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options : BA0,BA1,A11 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be asserted before at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data will
be available.
The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed
as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the
output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
相关PDF资料 |
PDF描述 |
|---|---|
| GLT5640L32-10 | CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-5 | CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-5.5 | CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-6 | CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-7 | 12 AMP MINIATURE POWER RELAY |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GLT5640L32-10 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-5.5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-6 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM |
| GLT5640L32-7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:CMOS Synchronous DRAM 2M x 32 SDRAM |
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