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参数资料
| 型号： | GLT725608-20J3 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ultra High Performance 32K x 8 Bit CMOS STATIC RAM |
| 中文描述： | 32K的超高性能× 8位CMOS静态RAM |
| 文件页数： | 7/12页 |
| 文件大小： | 1119K |
| 代理商： | GLT725608-20J3 |
G-LINK
GLT725608
Ultra High Performance 32K x 8 Bit CMOS STATIC RAM
Feb, 2001(Rev.2.4)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
Switching Waveform (Write Cycle)
WRITE CYCLE 2
(1,6)
Note:
1.
WE
must be high during address transitions.
2. The internal write time of the memory is defined by the overlap
CE
low and
WE
low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.
3. T
WR
is measured from the earlier of
CE
or
WE
going high at the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the
CE
low transition occurs simultaneously with the
WE
low transitions or after the
WE
transition, outputs remain in a high impedance state.
6.
OE
is continuously low (
OE
=V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If
CE
is low during this period, I/O pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured
±
200mV from steady state with C
L
=5pF.
11. t
CW
is measured from
CE
going low to the end of write.
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