- 您现在的位置：买卖IC网 > PDF目录383009 > GM3110 (Electronic Theatre Controls, Inc.) XGA/SXGA LCD Controller PDF资料下载
参数资料
| 型号： | GM3110 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件页数： | 12/51页 |
| 文件大小： | 1379K |
| 代理商： | GM3110 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
5
C5110-DAT-01C
Table 2. DVI Input Port
Pin Name
No I/O Description
AVDD_IMB
173
AP
Analog VDD (3.3V) for internal biasing circuits.
Must be bypassed with decoupling capacitors (as close as possible to the pin).
External reference resistor.
An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin.
Analog GND for internal biasing circuits.
Must be connected directly to the ground plane.
VDD (2.5V) for DVI input pair 2 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX2 pin (as close as possible to the pin).
GND for DVI input pair 2 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 2 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 2
DVI input pair 2
Analog VDD (3.3V) for DVI input pair 2 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX2 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 1 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX1 pin (as close as possible to the pin).
GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
Analog GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 1
DVI input pair 1
Analog VDD (3.3V) for DVI input pair 1 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX1 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 0 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX0 pin (as close as possible to the pin).
GND for DVI input pair 0 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 0 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 0
DVI input pair 0
Analog VDD (3.3V) for DVI input pair 0 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX0 pin (as close as possible to the pin).
DVI input clock pair
DVI input clock pair
Analog VDD (3.3V) for DVI input clock pair input buffer. Must be bypassed with 100pF
capacitor to AGND_RXC pin (as close as possible to the pin).
Analog GND for DVI input clock pair input buffer.
Must be connected directly to the analog ground plane.
Digital GND for the DVI receiver internal PLL.
Must be connected directly to the system ground plane.
Analog VDD (2.5V) for the DVI receiver internal PLL. Must be bypassed with a decoupling
capacitor to AGND_RXPLL pin (as close as possible to the pin).
For test purposes only. Do not connect.
REXT
174
AI
AGND_IMB
175
AG
VDD_RX2_2.5
176
P
GND_RX2
177
G
AGND_RX2
178
AG
RX2+
RX2-
AVDD_RX2
179
180
181
AI
AI
AP
VDD_RX1_2.5
182
P
GND_RX1
183
G
AGND_RX1
184
AG
RX1+
RX1-
AVDD_RX1
185
186
187
AI
AI
AP
VDD_RX0_2.5
188
P
GND_RX0
189
G
AGND_RX0
190
AG
RX0+
RX0-
AVDD_RX0
191
192
193
AI
AI
AP
RXC+
RXC-
AVDD_RXC
194
195
196
AI
AI
AP
AGND_RXC
197
AG
GND_RXPLL
198
G
VDD_RXPLL_2.5
199
AP
CLKOUT
201
AO
Table 3. RCLK PLL Pins
No I/O Description
Pin Name
AVDD_RPLL
150
AP
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator, or from single-ended
CMOS/TTL clock oscillator (refer to Figure 7). This is a 5V-tolerant input.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
AVSS_RPLL
149
AG
TCLK
152
AI
XTAL
VDD_RPLL
VSS_RPLL
151
148
147
AO
P
G
相关PDF资料 |
PDF描述 |
|---|---|
| GM3120 | XGA/SXGA LCD Controller |
| GM5110 | XGA/SXGA LCD Controller |
| GM5110-H | XGA/SXGA LCD Controller |
| GM5120 | XGA/SXGA LCD Controller |
| GM5120-H | XGA/SXGA LCD Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GM3120 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:XGA/SXGA LCD Controller |
| GM317 | 制造商:GAMMA 制造商全称:GAMMA 功能描述:3-TERMINAL 1.5A ADJUSTABLE REGULATOR |
| GM317_12 | 制造商:GAMMA 制造商全称:GAMMA 功能描述:3-TERMINAL 1.5A ADJUSTABLE REGULATOR |
| GM317L | 制造商:GAMMA 制造商全称:GAMMA 功能描述:3-TERMINAL 100mA ADJUSTABLE REGULATOR |
| GM317LS8RG | 制造商:GAMMA 制造商全称:GAMMA 功能描述:3-TERMINAL 100mA ADJUSTABLE REGULATOR |
发布紧急采购，3分钟左右您将得到回复。