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参数资料
| 型号： | GM3255S8T |
| 厂商： | American Power Management Inc. |
| 元件分类： | DC/DC变换器 |
| 英文描述： | 1.5A 280kHz DC-DC CONVERTOR BOOST REGULATOR |
| 中文描述： | 1.5A的为280kHz的DC - DC转换器升压稳压器 |
| 文件页数： | 17/19页 |
| 文件大小： | 234K |
| 代理商： | GM3255S8T |
APPLICATION INFORMATION
Current Mode Control
GM3255 family incorporates a current mode control
scheme. In which the PWM ramp signal is derived from
the power switch current. This ramp signal is compared
to the output of the error amplifier to control the on-time
power switch. The oscillator is used as a fixed-
frequency clock to ensure a constant operational fre-
quency. The resulting control scheme features several
advantages over conventional voltage mode control.
First, derived directly from the inductor, the ramp signal
responds immediately to line voltage changes. This
eliminates the delay caused by the output filter and er-
ror amplifier, which is commonly found in voltage mode
controllers. The second benefit comes from inherent
pulse-by pulse current limiting by merely clamping the
peak switching current. Finally, current mode com-
mands an output current rather than voltage, then the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher gain-
bandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, and
mainly subharmonic oscillation at duty cycles over 50%.
The GM3255 family solves this problem by adopting a
slope compensation scheme, in which, a fixed ramp
generated by the oscillator is added to the current
ramp. A
proper slope rate is provided to improve circuit
stability without sacrificing the advantages of current
mode control.
Oscillator and Shutdown
Shown in Figure 6. The power switch is turned off
by the output of the PWM Comparator.
A TTL-compatible sync input at the SS pin is capa-
ble of syncing up to 1.8 times the base oscillator fre-
quency.
As shown in Figure 7, in order to sync to a
higher frequency, a positive transition turns on the
power switch before the output of the oscillator goes
high, thereby resetting the oscillator. The sync oper-
ation allows multiple power supplies to operate at
the same frequency.
A sustained logic low at the SS pin will shut down
the IC and reduce the supply current.
An additional feature includes frequency shift to
20% of the nominal frequency when either the NFB
or FB pins trigger the threshold. During power up,
overload, or short circuit conditions, the minimum
switch on-time is limited by the PWM comparator
minimum pulse width. Extra switch off-time reduces
the minimum duty cycle to protect external compo-
nents and the IC itself.
As Previously mentioned, this block also produces a
ramp for the slope compensation to improve regula-
tor stability.
Error Amplifier
The FB pin is directly connected to the inverting in-
put of the positive error amplifier, whose non-
incerting input is fed by the 1.276V reference. The
amplifier is transconductance amplifier with a high
output impedance of approximately 1M W, as shown
in Figure 8. The V
pin is connected to the output of
C
the error amplifiers and is internally clamped be-
tween 0.5V and 1.7V . A typical connection at the
V
pin includes a capacitor in series with a resistor
C
to ground, forming a pole / zero for loop compensa-
tion.
An external shunt can be connected between the VC
pin and ground to reduce its clamp voltage.
Current
Ramp
VSW
Sync
S
Q
R
V
CC
L
D1
V
C
O
R
LOAD
Driver
63 m
Oscillator
PWM
Comparator
SUMMER
Slope Compensation
In Out
Power Switch
V
SW
X5
-
+
Figure 6. Current Mode Control Scheme
Figure 8. Error Amplifier Equivalent Circuit
+
-
CM3255
1MW
positive error-amp
1.276 V
FB
VC
C1
R1
5 kW
0.01F
Voltage
Clamp
120pF
G
M
3
2
5
7
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