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参数资料
| 型号： | GM72V66841ELT-7K |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封装： | 0.400 INCH, TSOP2-54 |
| 文件页数： | 14/57页 |
| 文件大小： | 592K |
| 代理商： | GM72V66841ELT-7K |
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LG Semicon
GM72V66841CT/CLT
From [WRITE with AUTO-Precharge]
To [DESL], [NOP]:
These commands
continue write operations until the burst
operation is completed, and the synchronous
DRAM then enters Precharge mode.
To [ACTV]:
This command makes the other
bank active. (However, an interval of
t
RC
is
required.) Attempting to make the currently
active bank active results in an illegal
command.
To [DESL], [NOP], [BST]:
After an auto-
refresh cycle (after
t
RC
), the synchronous
DRAM automatically enters the Idle state.
From [REFRESH]
13
From [WRITE]
To [DESL], [NOP]:
These commands
continue write operations until the burst
operation is completed.
To [BST]:
This command stops a full-page
burst.
To [READ], [READ A]:
These commands
stop a burst and start a read cycle.
To [WRIT], [WRIT A]:
These commands
stop a burst and start the next write cycle.
To [ACTV]:
This command makes the
other bank active. (However, an interval of
t
RRD
is required.) Attempting to make the
currently active bank active results in an
illegal command.
To [PRE], [PALL]:
These commands stop
burst write and the synchronous DRAM
then enters Precharge mode.
From [READ]
From [READ with AUTO-Precharge]
To [DESL], [NOP]:
These commands
continue read operations until the burst
operation is completed, and the synchronous
DRAM then enters Precharge mode.
To [ACTV]:
This command makes other
banks bank-active. (However, an interval of
t
RRD
is required.) Attempting to make the
currently active bank active results in an
illegal command.
To [DESL], [NOP]:
These commands
continue read operations until the burst
operation is completed.
To [BST]:
This command stops a full-page
burst.
To [READ], [READ A]:
Data output by the
previous read command continues to be
output. After CAS latency, the data output
resulting from the next command will start.
To [WRIT], [WRIT A
]
:
These commands
stop a burst read, and start a write cycle.
To [ACTV]:
This command makes other
banks bank-active. (However, an interval of
t
RRD
is required.) Attempting to make the
currently active bank active results in an
illegal command.
To [PRE], [PALL]:
These commands stop a
burst read, and the synchronous DRAM
enters Precharge mode.
相关PDF资料 |
PDF描述 |
|---|---|
| GM72V66841ELT-8 | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841Exx | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ELT-7 | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ELT-75 | 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GM72V66841ELT-8 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET-7 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM |
| GM72V66841ET-75 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SDRAM |
| GM72V66841ET-7J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 SDRAM |
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