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| 型号： | GMZAN3L |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶显示器接口控制器 |
| 文件页数： | 21/53页 |
| 文件大小： | 556K |
| 代理商： | GMZAN3L |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
28
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
4.3.2 ADC Characteristics
The table below summarizes the characteristics of the ADC:
Table 15.
ADC Characteristics
MIN
TYP
MAX
NOTE
Track & Hold Amp Bandwidth
290 MHz Guaranteed. Note that the Track & Hold Amp
Bandwidth is programmable. 290 MHz is the
maximum setting.
Full Scale Adjust Range at RGB Inputs
0.55 V
0.90 V
Full Scale Adjust Sensitivity
+/- 1 LSB
Measured at ADC Output.
Independent of full scale RGB input.
Zero Scale Adjust Sensitivity
+/- 1 LSB
Measured at ADC Output.
Sampling Frequency (Fs)
10 MHz
100 MHz
Differential Non-Linearity (DNL)
+/-0.5 LSB
+/-0.9 LSB Fs = 100 MHz
No Missing Codes
Guaranteed by test.
Integral Non-Linearity (INL)
+/- 1.5 LSB
Fs =100 MHz
Channel to Channel Matching
+/- 0.5 LSB
Note that input formats with resolutions or refresh rates higher than that supported by the LCD panel are
supported as recovery modes only. This is called RealRecovery. For example, it may be necessary to
shrink the image. This may introduce image artifacts. However, the image is clear enough to allow the
user to change the display properties.
The gmZAN3 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors
(about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and
width are programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample
analog RGB data (ACLK). This circuit is locked to HSYNC of the incoming video signal.
Patented digital clock synthesis technology makes the gmZAN3 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit
can generate any ACLK clock frequency within the range of 10 MHz to 100 MHz.
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