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参数资料
| 型号： | GS8160E36GT-250 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 512K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 1/25页 |
| 文件大小： | 647K |
| 代理商： | GS8160E36GT-250 |
GS8160E18/32/36T-250/225/200/166/150/133
1M x 18, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 2.13 11/2004
1/25
1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Dual Cycle Deselect (DCD) operation
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS8160E18/32/36T is an 18,874,368-bit (16,777,216-bit for x32
version) high performance synchronous SRAM with a 2-bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW)
are synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8160E18/32/36T is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS8160E18/32/36T operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
3.3 V
Curr (x18)
Curr (x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
2.5 V
Curr (x18)
Curr (x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
6.0
6.5
7.0
7.5
8.5
ns
3.3 V
Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
2.5 V
Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
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| GS8162Z72CGC-250IVT | 256K X 72 ZBT SRAM, 5.5 ns, PBGA209 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8160E36T-133 | 制造商:GSI 功能描述: 制造商:GSI Technology 功能描述: |
| GS8160E36T-133I | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Sync Burst SRAMs |
| GS8160E36T-150 | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Sync Burst SRAMs |
| GS8160E36T-150I | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Sync Burst SRAMs |
| GS8160E36T-166 | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Sync Burst SRAMs |
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