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参数资料
| 型号： | GS8161E32D-225I |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 20-Bit SSTL_3 Interface Buffer With 3-State Outputs 64-TSSOP 0 to 70 |
| 中文描述： | 100万× 18，512k × 32的，为512k × 36 35.7同步突发静态存储器 |
| 文件页数： | 15/36页 |
| 文件大小： | 939K |
| 代理商： | GS8161E32D-225I |
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
15/36
1998, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
tZZR
tZZH
tZZS
tKL
tKH
tKC
CK
ZZ
相关PDF资料 |
PDF描述 |
|---|---|
| GS8161E32D-250 | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E32D-250I | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E36D-133 | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E36D-133I | 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70 |
| GS8161E36D-150 | 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8161E32D-250 | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E32D-250I | 制造商:GSI 制造商全称:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E32DD-150 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161E32DD-400 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161E32DGT-200 | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
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