参数资料
型号: GS8161E36D-225
厂商: Electronic Theatre Controls, Inc.
英文描述: 25-Bit Configurable Registered Buffer With Address-Parity Test 96-LFBGA 0 to 70
中文描述: 100万× 18,512k × 32的,为512k × 36 35.7同步突发静态存储器
文件页数: 18/36页
文件大小: 939K
代理商: GS8161E36D-225
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
18/36
1998, GSI Technology
Capacitance
(T
A
= 25
o
C, f = 1 MH
Z
, V
DD
= 2.5 V)
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Symbol
C
IN
C
I/O
Test conditions
V
IN
= 0 V
V
OUT
= 0 V
Typ.
Max.
Unit
Input Capacitance
4
5
pF
Input/Output Capacitance
6
7
pF
Parameter
Conditions
V
DD
– 0.2 V
0.2 V
1 V/ns
V
DD
/2
V
DDQ
/2
Fig. 1
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
Device is deselected as defined by the Truth Table.
3.
50% tKC
V
SS
2.0 V
50%
V
SS
V
IH
Undershoot Measurement and Timing
Overshoot Measurement and Timing
50% tKC
V
DD
+ 2.0 V
50%
V
DD
V
IL
DQ
V
DDQ/2
50
30pF
*
Output Load 1
* Distributed Test Jig Capacitance
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