- 您现在的位置：买卖IC网 > PDF目录383031 > GS8161Z36D-225 (Electronic Theatre Controls, Inc.) 1024 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 PDF资料下载
参数资料
| 型号： | GS8161Z36D-225 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | DRAM |
| 英文描述： | 1024 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
| 中文描述： | 35.7流水线和流量，通过同步唑的SRAM |
| 文件页数： | 10/36页 |
| 文件大小： | 939K |
| 代理商： | GS8161Z36D-225 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
10/36
1998, GSI Technology
Synchronous Truth Table
Operation
Type
Address
CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
DQ
Notes
Read Cycle, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
L
L
Q
Read Cycle, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
L
L
Q
1,10
NOP/Read, Begin Burst
R
External
L-H
L
L
H
X
L
H
L
H
L
High-Z
2
Dummy Read, Continue Burst
B
Next
L-H
L
H
X
X
X
X
X
H
L
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L-H
L
L
L
L
L
H
L
X
L
D
3
Write Cycle, Continue Burst
B
Next
L-H
L
H
X
L
X
X
X
X
L
D
1,3,10
Write Abort, Continue Burst
B
Next
L-H
L
H
X
H
X
X
X
X
L
High-Z 1,2,3,10
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
H
X
X
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
X
H
X
L
High-Z
Deselect Cycle, Power Down
D
None
L-H
L
L
X
X
X
L
X
X
L
High-Z
Deselect Cycle
D
None
L-H
L
L
L
H
L
H
L
X
L
High-Z
1
Deselect Cycle, Continue
D
None
L-H
L
H
X
X
X
X
X
X
L
High-Z
1
Sleep Mode
None
X
X
X
X
X
X
X
X
X
H
High-Z
Clock Edge Ignore, Stall
Current
L-H
H
X
X
X
X
X
X
X
L
-
4
Notes:
1.
Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
2.
3.
4.
5.
6.
7.
8.
9.
相关PDF资料 |
PDF描述 |
|---|---|
| GS8161Z36D-225I | 1024 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
| GS8161Z36D-225T | 1024 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
| GS8161Z36D-250 | 1024 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
| GS8161Z36D-250I | 2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
| GS8161Z36D-250IT | 2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8161Z36D-225I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36D-225IT | 制造商:GSI 制造商全称:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36D-225T | 制造商:GSI 制造商全称:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36D-250 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36D-250I | 制造商:GSI 制造商全称:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
发布紧急采购，3分钟左右您将得到回复。