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参数资料
| 型号： | GS832032AGT-200 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | CACHE SRAM, PQFP100 |
| 封装： | ROHS COMPLIANT, TQFP-100 |
| 文件页数： | 1/23页 |
| 文件大小： | 583K |
| 代理商： | GS832032AGT-200 |
Preliminary
GS832018/32/36AGT-400/375/333/250/200/150
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
400 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.00a 2/2011
1/23
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Single Cycle Deselect (SCD) operation
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
RoHS-compliant 100-lead TQFP package
Functional Description
Applications
The GS832018/32/36AGT is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36AGT operates on a 3.3 V or 2.5 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-400
-375
-333
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
2.66
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
355
440
340
415
335
385
245
310
205
265
165
215
mA
Flow
Through
2-1-1-1
tKQ
tCycle
4.0
4.2
4.5
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
245
310
235
300
225
285
190
250
165
225
155
205
mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS832032AGT-250 | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
| GS832032AGT-250I | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
| GS832032AGT-250IV | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
| GS832032AGT-250V | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
| GS832032AGT-333 | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
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