- 您现在的位置：买卖IC网 > PDF目录385318 > GS832136GE-250IV (GSI TECHNOLOGY) 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs PDF资料下载
参数资料
| 型号： | GS832136GE-250IV |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | DRAM |
| 英文描述： | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| 中文描述： | 1M X 36 CACHE SRAM, 5.5 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件页数： | 1/31页 |
| 文件大小： | 745K |
| 代理商： | GS832136GE-250IV |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
GS832118/32/36E-xxxV
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Commercial Temp
Industrial Temp
Rev: 1.04 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/31
2003, GSI Technology
Features
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 165-bump FP-BGA package
RoHS-compliant 165-bump BGA package available
Functional Description
Applications
The GS832118/32/36E-xxxV is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS832118/32/36E-xxxV is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832118/32/36E-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible.
Separate output power (V
DDQ
) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
3.0
4.0
4.4
5.0
6.0
285
350
320
295
260
6.5
6.5
7.0
7.5
8.0
205
235
225
210
200
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
3.0
3.0
3.5
3.8
6.6
210
240
8.5
8.5
165
190
4.0
7.5
185
215
8.5
8.5
155
175
ns
ns
mA
mA
ns
ns
mA
mA
265
245
220
Flow
Through
2-1-1-1
7.0
7.5
8.0
195
185
175
相关PDF资料 |
PDF描述 |
|---|---|
| GS832136GE-250V | 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8322V72GC-250I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V18GE-225 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V18GE-225I | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
| GS8322V18GE-250 | 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS832136GE-250V | 制造商:GSI 制造商全称:GSI Technology 功能描述:2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs |
| GS8321E18AD-250 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8321E18AD-375 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8321E18AGD-375 | 制造商:GSI Technology 功能描述:165 FPBGA - Bulk |
| GS8321E18AGD-375I | 制造商:GSI Technology 功能描述:165 FPBGA - Bulk |
发布紧急采购，3分钟左右您将得到回复。