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参数资料
| 型号： | GS8342D09E-200T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 4M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/37页 |
| 文件大小： | 1668K |
| 代理商： | GS8342D09E-200T |
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Preliminary
GS8342D08/09/18/36E-333/300/250/200/167
36Mb SigmaQuad-II
Burst of 4 SRAM
167 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02 8/2005
1/37
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 4 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
SigmaQuad Family Overview
The GS8342D08/09/18/36E are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D08/18/36E SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B4 RAMs always transfer
data in four packets, A0 and A1 are internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfers. Because the LSBs are tied off internally,
the address field of a SigmaQuad-II B4 RAM is always two
address pins less than the advertised index depth (e.g., the 2M
x 18 has a 512K addressable index).
Parameter Synopsis
- 333
-300
-250
-200
-167
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.50 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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PDF描述 |
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| GS8342D09GE-250IT | 4M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8342D10BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D10BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D11BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D11BD-400 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D11BD-450 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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