- 您现在的位置：买卖IC网 > PDF目录223865 > GS8342D11BD-550IT (GSI TECHNOLOGY) 4M X 9 QDR SRAM, 0.45 ns, PBGA165 PDF资料下载
参数资料
| 型号： | GS8342D11BD-550IT |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/31页 |
| 文件大小： | 950K |
| 代理商： | GS8342D11BD-550IT |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
Preliminary
GS8342D06/11/20/38BD-550/500/450/400/350
36Mb SigmaQuad-II+TM
Burst of 4 SRAM
550 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 4/2011
1/31
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
2.5 Clock Latency
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 4 Read and Write
On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad-II Family Overview
The GS8342D06/11/20/38BD are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D06/11/20/38BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D06/11/20/38BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B4 RAMs always
transfer data in four packets, A0 and A1 are internally set to 0
for the first read or write transfer, and automatically
incremented by 1 for the next transfers. Because the LSBs are
tied off internally, the address field of a SigmaQuad-II+ B4
RAM is always two address pins less than the advertised index
depth force return (e.g., the 2M x 18 has a 512K addressable
index).
Parameter Synopsis
-550
-500
-450
-400
-350
tKHKH
1.81 ns
2.0 ns
2.2 ns
2.5 ns
2.86 ns
tKHQV
0.45 ns
相关PDF资料 |
PDF描述 |
|---|---|
| GS8342D37BD-300I | 1M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342QT07BD-357 | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342QT10BGD-300T | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342TT06BGD-500T | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| GS841Z36CGT-166IT | 128K X 36 ZBT SRAM, 7 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS8342D18AE-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FPBGA - Trays |
| GS8342D18AE-333 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FPBGA - Trays |
| GS8342D18AGE-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FPBGA - Trays |
| GS8342D18AGE-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FPBGA - Trays |
| GS8342D18BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
发布紧急采购，3分钟左右您将得到回复。