参数资料
型号: GS8640Z36GT-250
厂商: GSI TECHNOLOGY
元件分类: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 2M X 36 ZBT SRAM, 6.5 ns, PQFP100
封装: ROHS COMPLIANT, TQFP-100
文件页数: 1/25页
文件大小: 618K
代理商: GS8640Z36GT-250
Product Preview
GS8640Z18/36T-300/250/200/167
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz
167 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.01 1/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/25
2004, GSI Technology
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
2.5 V or 3.3 V +10%/
10% core power supply
2.5 V or 3.3 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8640Z18/36T is a 72Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8640Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8640Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-300
2.3
3.3
400
480
5.5
5.5
285
330
-250
2.5
4.0
340
410
6.5
6.5
245
280
-200
3.0
5.0
290
350
7.5
7.5
220
250
-167
3.5
6.0
260
305
8.0
8.0
210
240
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Flow
Through
2-1-1-1
*All GSI Technology packages are at least 5/6 RoHS compliant.
Packages listed with the additional “G” designator are 6/6 RoHS compliant.
相关PDF资料
PDF描述
GS8640Z36GT-300 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z36T-167 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z36T-167I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z36T-200 72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z36T-200I 72Mb Pipelined and Flow Through Synchronous NBT SRAM
相关代理商/技术参数
参数描述
GS8640Z36GT-250IV 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 72MBIT 2MX36 6.5NS/3NS 100TQFP - Trays
GS8640Z36GT-250V 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 72MBIT 2MX36 6.5NS/3NS 100TQFP - Trays
GS8640Z36GT-300 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8640Z36GT-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 72MBIT 2MX36 5.5NS/2.3NS 100TQFP - Trays
GS8640Z36T-167 制造商:GSI 制造商全称:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM