参数资料
型号: GS864272GC-250V
厂商: GSI TECHNOLOGY
元件分类: DRAM
英文描述: 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
中文描述: 1M X 72 CACHE SRAM, 6.5 ns, PBGA209
封装: 14 X 22 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209
文件页数: 28/35页
文件大小: 934K
代理商: GS864272GC-250V
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
110
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
Preliminary
GS864218/36/72(B/C)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 6/2006
28/35
2004, GSI Technology
相关PDF资料
PDF描述
GS864218B-167V 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS864218B-200IV 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS864218B-200V 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS864218B-250IV 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
GS864218B-250V 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
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