参数资料
型号: GS8642Z18GB-300
厂商: GSI TECHNOLOGY
元件分类: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 4M X 18 ZBT SRAM, 5.5 ns, PBGA119
封装: 14 X 22 MM, 1.27 MM PITCH, ROHS COMPLIANT, FPBGA-119
文件页数: 28/34页
文件大小: 872K
代理商: GS8642Z18GB-300
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
3.3 V Test Port Input High Voltage
V
IHJ3
2.0
V
DD3
+0.3
V
1
3.3 V Test Port Input Low Voltage
V
ILJ3
0.3
0.8
V
1
2.5 V Test Port Input High Voltage
V
IHJ2
0.6 * V
DD2
V
DD2
+0.3
V
1
2.5 V Test Port Input Low Voltage
V
ILJ2
0.3
0.3 * V
DD2
V
1
TMS, TCK and TDI Input Leakage Current
I
INHJ
300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I
INLJ
1
100
uA
3
TDO Output Leakage Current
I
OLJ
1
1
uA
4
Test Port Output High Voltage
V
OHJ
1.7
V
5, 6
Test Port Output Low Voltage
V
OLJ
0.4
V
5, 7
Test Port Output CMOS High
V
OHJC
V
DDQ
– 100 mV
V
5, 8
Test Port Output CMOS Low
V
OLJC
100 mV
V
5, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Input Under/overshoot voltage must be
2 V > Vi < V
DDn
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
V
ILJ
V
IN
V
DDn
0 V
V
IN
V
ILJn
Output Disable, V
OUT
= 0 to V
DDn
The TDO output driver is served by the V
DDQ
supply.
I
OHJ
=
4 mA
I
OLJ
= + 4 mA
I
OHJC
= –100 uA
I
OLJC
= +100 uA
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
28/34
2004, GSI Technology
JTAG Port AC Test Conditions
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Parameter
Conditions
Input high level
V
DD
– 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
V
DDQ
/2
Output reference level
V
DDQ
/2
DQ
V
DDQ
/2
50
30pF
*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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