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参数资料
| 型号： | GS88118AGT-150I |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 7.5 ns, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 1/36页 |
| 文件大小： | 915K |
| 代理商： | GS88118AGT-150I |
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GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
512K x 18, 256K x 36
9Mb Synchronous Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04 3/2005
1/36
2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
IEEE 1149.1 JTAG-compatible Boundary Scan
2.5 V or 3.3 V +10%/–10% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard packages
Functional Description
Applications
The GS88118/36AT/D is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118/36AT/D is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118/36AT/D operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
Curr (x18)
Curr (x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
6.0
6.5
7.0
7.5
8.5
ns
Curr (x18)
Curr (x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
相关PDF资料 |
PDF描述 |
|---|---|
| GS88118AGT-133T | 512K X 18 CACHE SRAM, 8.5 ns, PQFP100 |
| GS88136BD-333 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88136BD-333I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88136BGD-150 | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
| GS88136BGD-150I | 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS88118AT | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
| GS88118AT-133 | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
| GS88118AT-133I | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
| GS88118AT-150 | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
| GS88118AT-150I | 制造商:GSI 制造商全称:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs |
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