
GSC93BC46/56/66
Page: 2/8
ISSUED DATE :2006/06/14
REVISED DATE :
Figure 2. Block Diagram
The interface foe the GSC93BC46/56/66 is accessed through four different signals:
Chip Select (CS), Data Input (DI), Data Output (DO), and Serial Data Clock (SK). The Chip Select (CS) signal
must be pulled high before issuing a command through the Data Input (DI) pin. The Serial Data Clock (SK)
signal is used in conjunction with the Data Input (DI) pin.
PIN Capacitance
Applicable over recommended operating range from TA=25 : , f=1.0MHz, Vcc=+5V
Symbol
Test Condition
Max
Unit
Condition
COUT
Output Capacitance (DO)
5
pF
VOUT=0V
CIN
Input Capacitance (CK, SK, DI)
5
pF
VIN=0V
Note: 1. This parameter is characterized and not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TA=-40 ~ +85 : , Vcc=+1.8 ~ +5V (unless otherwise noted)
Parameter
Symbol
Test Condition
Min
TYP
Max
Unit
Supply Voltage
VCC1
1.8
-
5.5
V
Supply Voltage
VCC2
2.7
-
5.5
V
Supply Voltage
VCC3
4.5
-
5.5
V
Supply Current VCC=5.0V
ICC
READ at 1MHz
-
0.5
2.0
mA
Supply Current VCC=5.0V
ICC
WRITE at 1MHz
-
0.5
2.0
mA
Standby Current VCC=1.8V
ISB1
CS=0V
-
0
0.1
A
Standby Current VCC=2.7V
ISB2
CS=0V
-
6.0
10.0
A
Standby Current VCC=5.0V
ISB3
CS=0V
-
17
30
A
Input Leakage Current
ILI
VIN=0V to VCC
-
0.1
3.0
A
Output Leakage Current
ILO
VIN=0V to VCC
-
0.1
3.0
A
Input Low Level
Input High Level
VIL1(1)
VIH1(1) 2.7V< V
CC
<5.5V
-0.6
2.0
-
0.8
VCC+1
V
Input Low Level
Input High Level
VIL2(1)
VIH2(1) 1.8V< V
CC
<2.7V
-0.6
VCCx0.7
-
VCCx0.3
VCC+1
V
Output Low Level
Output High Level
VOL1(1)
VOH1(1)
2.7V< VCC <5.5V; IOL=2.1mA
IOH=-0.4mA
-
2.4
-
0.4
-
V
Output Low Level
Output High Level
VOL2(1)
VOH2(1)
1.8V< VCC <2.7V; IOL=0.15mA
IOH=-100uA
-
VCC-2
-
0.2
-
V
Note 1: VIL and VIH max are reference only and are not tested.
Notes
1. The ORG pin is used to select between x8
and x16.
When the pin is connected to Vcc, x16 mode
is selected.
Otherwise, the ORG pin should be grounded
in order to select x8 mode.