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参数资料
| 型号： | GTLP8T306MTC |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 1/6页 |
| 文件大小： | 0K |
| 描述： | IC TRSVR 8BIT LVTTL/GTLP 24TSSOP |
| 标准包装： | 61 |
| 逻辑类型： | 收发器，非反相 |
| 元件数： | 1 |
| 每个元件的位元数： | 8 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
2000 Fairchild Semiconductor Corporation
DS500051
www.fairchildsemi.com
September 1997
Revised December 2000
GTLP8T3
06
8-
Bit
L
V
TTL/
GTLP
Bus
T
rans
ceiver
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device pro-
vides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different out-
put levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s VREF pin provides external supply reference voltage for
receiver threshold adjustibility
s Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s TTL compatible driver and control inputs
s Designed using Fairchild advanced CMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s 5V over voltage tolerance on LVTTL ports
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s A Port source/sink
24mA/+24mA
s B Port sink
+50mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
Package Description
GTLP8T306MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| GTLP8T306MTCX | 功能描述:总线收发器 8-Bit Bus Trans RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| GTLPBT306MTCX | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| GTLPH1612 | 制造商:TI 制造商全称:Texas Instruments 功能描述:18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER |
| GTLPH16612DGG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18-Bit Bus Transceiver |
| GTLPH16612DL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18-Bit Bus Transceiver |
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