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参数资料
| 型号： | HB52R649E1U-A6B |
| 厂商： | ELPIDA MEMORY INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 72 SYNCHRONOUS DRAM MODULE, 6.9 ns, DMA168 |
| 封装： | DIMM-168 |
| 文件页数： | 8/20页 |
| 文件大小： | 151K |
| 代理商： | HB52R649E1U-A6B |
EOL
Product
HB52R649E1U-A6B/B6B
Preliminary Data Sheet E0022H10
16
AC Characteristics (Ta = 0 to 55°C, V
CC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)
HB52R649E1U
-A6B/B6B
Parameter
Symbol
PC100
Symbol
Min
Max
Unit
Notes
Command setup time
t
CS
Tsi
2.6
—
ns
1
Command hold time
t
CH
Thi
1.6
—
ns
1
Ref/Active to Ref/Active command period t
RC
Trc
70
—
ns
1
Active to precharge command period
t
RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t
RCD
Trcd
20
—
ns
1
Precharge to active command period
t
RP
Trp
20
—
ns
1
Write recovery or data-in to precharge
lead time
t
DPL
Tdpl
10
—
ns
1
Active (a) to Active (b) command period
t
RRD
Trrd
20
—
ns
1
Transition time (rise to fall)
t
T
15ns
Refresh period
t
REF
—
64
ms
Notes: 1. AC measurement assumes t
T = 1 ns.
Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C
L = 50 pF.
3. t
LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t
HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t
CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
t
T
2.4 V
0.4 V
0.8 V
2.0 V
input
t
T
DQ
CL
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相关代理商/技术参数 |
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|---|---|
| HB52R649E1U-B6B | 制造商:ELPIDA 制造商全称:Elpida Memory 功能描述:512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM |
| HB52RD168DB-A6F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x64 SDRAM Module |
| HB52RD168DB-A6FL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x64 SDRAM Module |
| HB52RD168DB-B6F | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x64 SDRAM Module |
| HB52RD168DB-B6FL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x64 SDRAM Module |
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