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参数资料
| 型号： | HCMS-2919 |
| 元件分类： | 显示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, BLUE, 3.71 mm |
| 文件页数： | 2/14页 |
| 文件大小： | 139K |
| 代理商： | HCMS-2919 |
10
Serial/Simultaneous Data Output D0
Bit D0 of control word 1 is used to switch the mode of
DOUT between serial and simultaneous data entry
during Control Register writes. The default mode (logic
low) is the serial DOUT mode. In serial mode, DOUT is
connected to the last bit D7 of the Control Shift
Register.
Storing logic high to bit D0 changes DOUT to
simultaneous mode, which affects the Control Register
only. In simultaneous mode, DOUT is logically connected
to DIN. This arrangement allows multiple ICs to have
their Control Registers written to simultaneously. For
example, for n ICs in the serial mode, n * 8 clock pulses
to load the same data in all Control Registers. The
propagation delay from the first IC to the last is n *
tDOUTP.
External Oscillator Prescaler Bit D1
Bit D1 of Control Word 1 is used to scale the frequency
of an external Display Oscillator. When this bit is logic
low, the external Display Oscillator directly sets the
internal display clock rate. When this bit is a logic high,
the external oscillator is divided by 8. This scaled
frequency then sets the internal display clock rate. It
takes 512 cycles of the display clock (or 8 x 512 = 4096
cycles of an external clock with the divide by 8
prescaler) to completely refresh the display once. Using
the prescaler bit allows the designer to use a higher
external oscillator frequency without extra circuitry.
This bit has no affect on the internal Display Oscillator
Frequency.
Bits D2-D6
These bits must always be programmed to logic low.
Cascaded ICs
Figure 6 shows how two ICs are connected within an
HCMS-29XX display. The first IC controls the four left-
most characters and the second IC controls the four
right-most characters. The Dot Registers are connected
in series to form a 320-bit dot shift register. The location
of pixel 0 has not changed. However, Dot Shift Register
bit 0 of IC2 becomes bit 160 of the 320-bit dot shift
register.
The Control Registers of the two ICs are independent
of each other. This means that to adjust the display
brightness the same control word must be entered into
both ICs, unless the Control Registers are set to
simultaneous mode.
Longer character string systems can be built by
cascading multiple displays together. This is
accomplished by creating a five line bus. This bus
consists of CE, RS, BL, Reset, and CLK. The display pins
are connected to the corresponding bus line. Thus, all
CE pins are connected to the CE bus line. Similarly, bus
lines for RS, BL, Reset, and CLK are created. Then DIN is
connected to the right-most display. DOUT from this
display is connected to the next display. The left-most
display receives its DIN from the DOUT of the display to
its right. DOUT from the left-most display is not used.
Each display may be set to use its internal oscillator, or
the displays may be synchronized by setting up one
display as the master and the others as slaves. The
slaves are set to receive their oscillator input from the
master’s oscillator output.
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