参数资料
型号: HCPL2630W
厂商: Fairchild Optoelectronics Group
文件页数: 4/12页
文件大小: 0K
描述: OPTOCOUPLER LOG-OUT 2CH 8-DIP
标准包装: 1,000
电压 - 隔离: 2500Vrms
通道数: 2,单向
电流 - 输出 / 通道: 50mA
数据速率: 10Mbps
传输延迟高 - 低 @ 如果: 45ns @ 7.5mA
电流 - DC 正向(If): 30mA
输入类型: DC
输出类型: 开路集电极
安装类型: 通孔
封装/外壳: 8-DIP(0.400",10.16mm)
供应商设备封装: 8-DIP
包装: 管件
其它名称: HCPL-2630W
Electrical Characteristics (Continued)
Transfer Characteristics (T A = -40 to +85°C unless otherwise speci?ed)
Symbol
I OH
V OL
I FT
DC Characteristics
HIGH Level Output Current
LOW Level Output Current
Input Threshold Current
Test Conditions
V CC = 5.5V, V O = 5.5V,
I F = 250μA, V E = 2.0V (2)
V CC = 5.5V, I F = 5mA, V E = 2.0V,
I CL = 13mA (2)
V CC = 5.5V, V O = 0.6V, V E = 2.0V,
Min.
Typ.*
.35
3
Max.
100
0.6
5
Unit
μA
V
mA
I OL = 13mA
Isolation Characteristics (T A = -40°C to +85°C unless otherwise speci?ed.)
Symbol
I I-O
Characteristics
Input-Output Insulation
Test Conditions
Relative humidity = 45%,
Min.
Typ.*
Max.
1.0*
Unit
μA
Leakage Current
T A = 25°C, t = 5s,
V I-O = 3000 VDC (12)
V ISO
R I-O
Withstand Insulation Test
Voltage
Resistance (Input to Output)
RH < 50%, T A = 25°C,
I I-O ≤ 2μA, t = 1 min. (12)
V I-O = 500V (12)
2500
10 12
V RMS
?
C I-O
Capacitance (Input to Output)
f=
1MHz (12)
0.6
pF
*All Typicals at V CC = 5V, T A = 25°C
Notes:
1. The V CC supply to each optoisolator must be bypassed by a 0.1μF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V CC and GND pins of each device.
2. Each channel.
3. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
4. t PLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
5. t PHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
6. t r – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. t f – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. t ELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
9. t EHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
10. CM H – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
HIGH state (i.e., V OUT > 2.0V). Measured in volts per microsecond (V/μs).
11. CM L – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the
LOW output state (i.e., V OUT < 0.8V). Measured in volts per microsecond (V/μs).
12. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
?2005 Fairchild Semiconductor Corporation
6N137, HCPL2601, HCPL2611, HCPL2630, HCPL2631 Rev. 1.0.8
4
www.fairchildsemi.com
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