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参数资料
| 型号： | HD74LS280FPEL |
| 元件分类： | 算术逻辑单元 |
| 英文描述： | LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14 |
| 封装： | 5.50 X 10.06 MM, 1.27 MM PITCH, PLASTIC, SOP-14 |
| 文件页数： | 4/6页 |
| 文件大小： | 175K |
| 代理商： | HD74LS280FPEL |
HD74LS280
Rev.3.00, Jul.15.2005, page 4 of 5
Testing Method
Test Circuit
4.5V
Σ
even
Load circuit 1
Output
VCC
RL
CL
Input
P.G.
Zout = 50
See
Function
Table
A
B
C
D
E
F
G
H
I
Σ
odd
Same as Load Circuit 1.
Output
Notes:
1.
CL includes probe and jig capacitance.
2.
All diodes are 1S2074(H).
Waveform
tPLH
tPHL
VOH
VOL
0 V
3 V
VOH
VOL
tPHL
tPLH
10%
90%
1.3 V
10%
90%
Input
In phase output
Out of phase output
tTLH
tTHL
Note:
Input pulse; tTLH
≤ 15 ns, t
THL
≤ 6 ns, PRR = 1 MHz, duty cycle 50%.
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