参数资料
型号: HEC4040BT,118
厂商: NXP Semiconductors
文件页数: 11/14页
文件大小: 0K
描述: IC 12STAGE BINARY COUNTER 16SOIC
产品培训模块: Logic Packages
标准包装: 2,500
系列: 4000B
逻辑类型: 二进制计数器
方向:
元件数: 1
每个元件的位元数: 12
复位: 异步
触发器类型: 负边沿
电源电压: 4.5 V ~ 15.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SO
包装: 带卷 (TR)
其它名称: 935249730118
HEC4040BT-T
HEC4040BT-T-ND
HEF4040B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 17 November 2011
6 of 14
NXP Semiconductors
HEF4040B
12-stage binary ripple counter
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
For loads other than 50 pF at the nth output, use the slope given.
[3]
tt is the same as tTHL and tTLH.
tt
transition time
5 V
[3] 10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-20
40
ns
tW
pulse width
CP input HIGH;
minimum width;
5 V
5025-
ns
10 V
3015-
ns
15 V
2010-
ns
MR input HIGH;
minimum width;
5 V
4020-
ns
10 V
3015-
ns
15 V
2010-
ns
trec
recovery time
MR input;
5 V
4020-
ns
10 V
3015-
ns
15 V
2010-
ns
fmax
maximum
frequency
CP input;
5 V
1020-
MHz
10 V
1530-
MHz
15 V
2550-
MHz
Table 6.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6.
Symbol
Parameter
Conditions
VDD
Extrapolation formula[1]
Min
Typ
Max
Unit
Table 7.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power
dissipation
5 V
PD = 400 fi + (fo CL) VDD2
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(f
o CL) = sum of the outputs.
10 V
PD = 2000 fi + (fo CL) VDD2
15 V
PD = 5200 fi + (fo CL) VDD2
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