参数资料
型号: HEF4013BTT,118
厂商: NXP Semiconductors
文件页数: 14/16页
文件大小: 0K
描述: IC FLIP FLOP DUAL D-TYPE 14TSSOP
产品培训模块: Logic Packages
标准包装: 2,500
系列: 4000B
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 2
每个元件的位元数: 1
频率 - 时钟: 40MHz
延迟时间 - 传输: 30ns
触发器类型: 正边沿
输出电流高,低: 3.4mA,3.4mA
电源电压: 3 V ~ 15 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
HEF4013B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 21 November 2011
7 of 16
NXP Semiconductors
HEF4013B
Dual D-type flip-flop
[1]
Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas. CL is given in pF.
12. Waveforms
trec
recovery time
nSD input;
5 V
+15
5-
ns
10 V
15
0
-
ns
15 V
15
0
-
ns
nCD input;
5 V
40
25
-
ns
10 V
25
10
-
ns
15 V
25
10
-
ns
fclk(max)
maximum clock
frequency
5 V
7
14
-
MHz
10 V
14
28
-
MHz
15 V
20
40
-
MHz
Table 7.
Dynamic characteristics …continued
Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.
Symbol Parameter
Conditions
VDD
Extrapolation formula Min
Typ
Max
Unit
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
Typical formula
Where
PD
dynamic power dissipation
5 V PD = 850 fi + (fo CL) VDD2 Wfi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
(f
o CL) = sum of the outputs;
VDD = supply voltage in V.
10 V PD = 3600 fi + (fo CL) VDD2 W
15 V PD = 9000 fi + (fo CL) VDD2 W
Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9.
Fig 4.
Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
001aah016
0 V
th
tsu
1/fclk(max)
th
tsu
tf
tr
tW
VM
VI
VOH
VOL
VI
output nQ
input nCP
input nD
tt
tPHL
tPLH
VY
VX
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