参数资料
型号: HEF4059BP,652
厂商: NXP Semiconductors
文件页数: 4/6页
文件大小: 0K
描述: IC PROG DIV-BY-COUNTER 24DIP
产品培训模块: Logic Packages
标准包装: 360
系列: 4000B
逻辑类型: 除以 N
方向:
元件数: 1
每个元件的位元数: 16
复位: 异步
计数速率: 20MHz
触发器类型: 正边沿
电源电压: 4.5 V ~ 15.5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 24-DIP(0.600",15.24mm)
供应商设备封装: 24-DIP
包装: 管件
January 1995
4
Philips Semiconductors
Product specication
Programmable divide-by-n counter
HEF4059B
LSI
Figure 3 illustrates the operation of the counter in mode
÷ 8 starting from the preset state 3.
Fig.3 Total count of 3.
CP INPUT
Kc INPUT
(Ka, Kb = LOW)
internal state
of counter
O OUTPUT
If the ‘master preset’ mode is started two clock cycles or
less before an output pulse, the output pulse will appear at
the time due. If the ‘master preset’ mode is not used the
counter is preset in accordance with the ‘jam inputs when
the output pulse appears. A HIGH level at the latch enable
input (EL) will cause the counter output to go HIGH once
an output pulse occurs, and remain in the HIGH state until
EL input returns to LOW. If the EL input is LOW, the output
pulse will remain HIGH for only one cycle of the clock input
signal.
When Ka = L, Kb = H, Kc = L and EL = L, the counter
operates in the ‘preset inhibit’ mode, with which the
dividend of the counter is fixed to 10 000, independent of
the state of the jam inputs.
When in the same state of mode select inputs EL = H, the
counter operates in the normal
÷ 10 mode, however,
without the latch operation at the output.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
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HEF4059BTD 制造商:未知厂家 制造商全称:未知厂家 功能描述:Prescaler/Frequency Divider