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| 型号： | HFA1113 |
| 厂商： | Intersil Corporation |
| 英文描述： | 850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier(850MHz、低失真、输出限定可编程增益缓冲放大器) |
| 中文描述： | 是850MHz，低失真，输出限制，可编程增益，缓冲放大器（是850MHz，低失真，输出限定可编程增益缓冲放大器） |
| 文件页数： | 6/16页 |
| 文件大小： | 491K |
| 代理商： | HFA1113 |
6
FN1342.6
July 11, 2005
.
Limiting Operation
General
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (pins 8 and
5) of the amplifier. V
H
sets the upper output limit, while V
L
sets the lower clamp level. If the amplifier tries to drive the
output above V
H
, or below V
L
, the clamp circuitry limits the
output voltage at V
H
or V
L
(
±
the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 4 shows a simplified schematic of the HFA1113 input
stage, and the high clamp (V
H
) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (Q
X1
- Q
X2
)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V
-IN
- V
OUT
)/R
F
+ V
-IN
/R
G
This current is mirrored onto the high impedance node (Z) by
Q
X3
-Q
X4
, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by Q
P4
and Q
N4
. Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced to
only that small current (-I
BIAS
) required to keep the output at
the final voltage.
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(Q
N6
and Q
P6
) to set up the base voltage on Q
P5
.
Q
P5
begins to conduct whenever the high impedance node
reaches a voltage equal to Q
P5
’s base voltage + 2V
BE
(Q
P5
and Q
N5
). Thus, Q
P5
clamps node Z whenever Z reaches
V
H
. R
1
provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. Q
P5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:
I
CLAMP
= (V
-IN
- V
OUT
CLAMPED
)/300
+ V
-IN
/R
G
.
As an example, a unity gain circuit with V
IN
= 2V, and V
H
= 1V,
would have I
CLAMP
= (2V - 1V)/300
+ 2V/
∞
= 3.33mA
(R
G
=
∞
because -IN is floated for unity gain applications).
Note that I
CC
will increase by I
CLAMP
when the output is
clamp limited.
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
R
1
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
∞
(A
V
= +1)
OR 0
(A
V
= +2)
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
V
H
+IN
V
L
V+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
+1
+IN
V-
V+
Q
P1
Q
N1
V-
Q
N3
Q
P3
Q
P4
Q
N2
Q
P2
Q
N4
Q
P5
Q
N5
Z
V+
-IN
V
OUT
I
CLAMP
R
F
= 300
(INTERNAL)
Q
P6
Q
N6
V
H
R
1
50K
(30K
FOR V
L
)
300
R
(INTERNAL)
V
-IN
200
FIGURE 4. HFA1113 SIMPLIFIED V
H
CLAMP CIRCUITRY
HFA1113
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| HFA1113IB | 功能描述:IC BUFFER 850MHZ 8-SOIC RoHS:否 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:50 系列:LinCMOS™ 放大器类型:通用 电路数:4 输出类型:- 转换速率:0.05 V/µs 增益带宽积:110kHz -3db带宽:- 电流 - 输入偏压:0.7pA 电压 - 输入偏移:210µV 电流 - 电源:57µA 电流 - 输出 / 通道:30mA 电压 - 电源，单路/双路(±):3 V ~ 16 V，±1.5 V ~ 8 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:管件 产品目录页面:865 (CN2011-ZH PDF) 其它名称:296-1834296-1834-5 |
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