参数资料
型号: HFA135NH40
英文描述: 400V 135A HEXFRED Discrete Diode in a D-67 Half-Pak package
中文描述: 400V 135a条HEXFRED二极分立二极管在D - 67半白包
文件页数: 6/15页
文件大小: 188K
代理商: HFA135NH40
6
R
S
and C
L
form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
560MHz. By decreasing R
S
as C
L
increases (as illustrated in
the curve), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth still decreases
as the load capacitance increases.
Evaluation Board
The performance of the HFA1305IB (SOIC) may be
evaluated using the HA5025 Evaluation Board and a SOIC
to DIP adaptor like the Aries Electronics Part Number
14-350000-10. The SSOP version can be evaluated using
the OPAMPSSOPEVAL board.
The schematic for the SOIC amplifier 1 and the
HA5025EVAL board layout are shown in Figure 2 and Figure
3. Resistors R
F
, R
G
, and +R
S
may require a change to
values applicable to the HFA1305IB.
The schematic for the SSOP amplifier 1 and the
OPAMPSSOPEVAL board layout are shown in Figure 4 and
Figure 5. Resistors R
F
, R
G
, and +R
S
may require a change
to values applicable to the HFA1305IA.
To order evaluation boards (part number HA5025EVAL or
OPAMPSSOPEVAL), please contact your local sales office.
0
100
200
300
400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
S
)
150
250
350
50
A
V
= +2
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
+5V
10
μ
F
0.1
μ
F
GND
GND
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
-
+
R
F
R
G
FIGURE 2. EVALUATION BOARD SCHEMATIC FOR SOIC
50
+R
S
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT FOR SOIC
+5V
10
μ
F
0.1
μ
F
GND
GND
-5V
0.1
μ
F
10
μ
F
49.9
IN
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
-
+
FIGURE 4. EVALUATION BOARD SCHEMATIC FOR SSOP
49.9
R
F
R
G
+R
S
0
0
HFA1305
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