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参数资料
| 型号： | HFA3863IN96 |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封装： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件页数： | 30/39页 |
| 文件大小： | 305K |
| 代理商： | HFA3863IN96 |
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4-30
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR
Bits 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Carrier Sense 2 (CS2) scale factor (0-7.875 range) (000000 - 111111).
CONFIGURATION REGISTER 31 ADDRESS (3Eh) TX POWER CONTROL
Bits 7:1
Sets the transmit power. 7 bits to DAC input, -64 to 63 range.
Note: rising edge of TXPE is required for value in CR 31 to be applied to DAC.
Bit 0
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
Bit 7
Selection bit for DAC input test mode 7.
0 = Barker.
1 = Low rate I/Q samples.
Bit 6
force high rate mode.
0 = normal.
1 = force high rate mode.
Bit 5
Length Field counter.
0 = disable (non 802.11 systems, length field may be in bits not microseconds).
1 = enabled.
Bit 4
Tristate test bus and enable inputs.
0 = Normal.
1 = enable inputs on test bus.
Bit 3
Disable spread sequence for 1 and 2Mbps.
0 = Normal.
1 = disabled.
Bit 2
Disable scrambler.
0 = normal scrambler operation.
1 = scrambler disabled (taps set to 0).
Bit 1
PN generator enable (RX 44MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
Bit 0
PN generator enable (RX 22MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2
Bit 7
Coherent AGC disable.
0 = normal, enabled.
1 = disable.
Bit 6
Time Tracking Mode.
0 = enable detection of the Service field bit showing that the carrier and bit timing are locked to the same oscillator.
1 = disable detection and force locked time tracking.
Note. for automatic locked time tracking operation, bit 2 of the received Service field as well as bit 2 of CR6 of the receiver
must be a “1”.
Bit 5
DC offset compensation control. Final digital DC input offset compensation.
0 = enable DC offset compensation.
1 = disable DC offset compensation.
Bit 4
Bypass I/Q A/Ds.
0 = disable bypass.
1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed.
Bit 3
disable time adjust during packet. Note: this turns off bit tracking.
0 = normal.
1 = time tracking disabled (overrides bit 6 also).
HFA3863
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