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参数资料
| 型号： | HI-307 |
| 厂商： | Intersil Corporation |
| 英文描述： | 32 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | CMOS模拟开关 |
| 文件页数： | 6/11页 |
| 文件大小： | 117K |
| 代理商： | HI-307 |
6
FIGURE 2E. V
ANALOG
= 5V
FIGURE 2F. V
ANALOG
= 0V
FIGURE 2G. V
ANALOG
= -5V
FIGURE 2H. V
ANALOG
= -10V
NOTE:
15. If R
GEN
, R
L
or C
L
is increased, there will be proportional increases in rise and/or fall RC times.
FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (t
OPEN
)
Test Circuits and Waveforms
(Continued)
TIME (
μ
s)
5
0
0
0.4
0.8
1.2
1.6
O
V
GEN
= 5V
TIME (
μ
s)
5
0
0
0.4
0.8
1.2
1.6
O
V
GEN
= 0V
-5
TIME (
μ
s)
0
0
0.4
0.8
1.2
1.6
O
V
GEN
= -5V
-5
TIME (
μ
s)
0
0
0.4
0.8
1.2
1.6
O
V
GEN
= -10V
-5
-10
SWITCH TYPE
V
INH
HI-301, HI-303
5V
HI-307
15V
V+
D
2
R
L2
C
L2
V-
-15V
GND
LOGIC
INPUT
V
S2
= +3V
S
2
OUT 1
OUT 2
D
1
S
1
V
S1
= +3V
R
L1
C
L1
15V
LOGIC “1” = SWITCH ON
LOGIC
INPUT
0V
0V
SWITCH
OUTPUTS
V
INH
50%
50%
t
OPEN
50%
50%
0V
OUT 1
OUT 2
R
L1
= R
L2
= 300
C
L1
= C
L2
= 33pF
t
OPEN
HI-301 thru HI-307
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