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参数资料
| 型号： | HI-5700 |
| 厂商： | Intersil Corporation |
| 英文描述： | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8位，20 MSPS的闪光的A / D转换器 |
| 文件页数： | 11/12页 |
| 文件大小： | 746K |
| 代理商： | HI-5700 |
4-1501
HI-5700
Glossary of Terms
Aperture Delay
: Aperture delay is the time delay between
the external sample command (the rising edge of the clock)
and the time at which the signal is actually sampled. This
delay is due to internal clock path propagation delays.
Aperture Jitter
: This is the RMS variation in the aperture delay
due to variation of internal
φ
1 and
φ
2 clock path delays and
variation between the individual comparator switching times.
Differential Linearity Error (DNL)
: The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of ideal
midpoints of adjacent codes. The ideal spacing of each
midpoint is 1.0 LSB. The range of values possible is from -1.0
LSB (which implies a missing code) to greater than +1.0 LSB.
Full Power Input Bandwidth
: Full power input bandwidth is
the frequency at which the amplitude of the fundamental of
the digital output word has decreased 3dB below the
amplitude of an input sine wave. The input sine wave has a
peak-to-peak amplitude equal to the reference voltage. The
bandwidth given is measured at the specified sampling
frequency.
Full Scale Error (FSE)
: Full Scale Error is the difference
between the actual input voltage of the 254 to 255 code
transition and the ideal value of V
REF
+ - 1.5 LSB. This error
is expressed in LSBs.
Integral Linearity Error (INL)
: The integral linearity error is the
difference in LSBs between the measured code centers and
the ideal code centers. The ideal code centers are calculated
using a best fit line through the converter’s transfer function.
LSB
: Least Significant Bit = (V
REF
+ - V
REF
-)/256. All HI-
5700 specifications are given for a 15.6mV LSB size V
REF
+
= 4.0V, V
REF
- = 0.0V.
Offset Error (VOS)
: Offset error is the difference between the
actual input voltage of the 0 to 1 code transition and the ideal
value of V
REF
- + 0.5 LSB, V
OS
Error is expressed in LSBs.
Power Supply Rejection Ratio (PSRR)
: PSRR is
expressed in LSBs and is the maximum shift in code
transition points due to a power supply voltage shift. This is
measured at the 0 to 1 code transition point and the 254 to
255 code transition point with a power supply voltage shift
from the nominal value of 5.0V.
Signal to Noise Ratio (SNR)
: SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.
Signal to Noise and Distortion Ratio (SINAD)
: SINAD is
the ratio in dB of the RMS signal to the RMS sum of the
noise and harmonic distortion at specified input and
sampling frequencies.
Total Harmonic Distortion (THD)
: THD is the ratio in dBc of
the RMS sum of the first five harmonic components to the
RMS signal for a specified input and sampling frequency.
相关PDF资料 |
PDF描述 |
|---|---|
| HI-5700883 | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| HI3-5700J-5 | 8-Bit, 20 MSPS Flash A/D Converter |
| HI9P5700J-5 | 8-Bit, 20 MSPS Flash A/D Converter |
| HIF_IOCTL | Using Slow Peripherals with 29K Family Processors Using the HIF ioctl Service for Nonblocking Reads |
| HIF_SPEC | EZ-030 Demonstration Board Theory of Operation Host Interface (HIF) Specification |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HI-5700/883 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
| HI-5700883 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
| HI-5701 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:6-Bit, 30MSPS, Flash A/D Converter |
| HI-5701/883 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:6-Bit, 30 MSPS Flash A/D Converter |
| HI-5701_05 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:6-Bit, 30MSPS, Flash A/D Converter |
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