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参数资料
| 型号： | HI-8788PQI |
| 厂商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | ARINC INTERFACE DEVICE 16-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT |
| 中文描述： | 1 CHANNEL(S), SERIAL COMM CONTROLLER, PQFP32 |
| 封装： | PLASTIC, QFP-32 |
| 文件页数： | 2/7页 |
| 文件大小： | 135K |
| 代理商： | HI-8788PQI |
HI-8787, HI-8788
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
PIN
SYMBOL
FUNCTION
DESCRIPTION
28
561 SYNC
Dn
GND
A0
SLP1.5
WRITE
RESET
digital output
digital inputs
power supply
digital input
digital input
digital input
digital input
digital input
digital output
digital input
power supply
analog output
analog output
digital output
power supply
power supply
ARINC 561 Sync signal
Parallel 16 bit bus input
Ground
Load address, A0=0 for 1st data load, A0=1 for 2nd data load
Selects the slope of the line driver. High=1.5us
Write strobe. Loads data on rising edge.
Registers and sequencing logic initialized when low
Clock input for the transmitter
Goes high if the buffer register is empty
When high the 32nd bit output is odd parity
-10 volt rail
Line driver output - A side
Line driver output - B side
Serial output for ARINC 561 data
+10 volt rail
+5 volt rail, “one” level out of line driver, inverted for “zero”
1, 3-10,13-15, 29-32
11
12
16
17
18
19
20
21
22
23
24
25
26
27
XMIT CLK
XMT RDY
PARITY ENB
V-
TXAOUT
TXBOUT
561 DATA
V+
VCC
The HI-8787 is a parallel to serial converter, which when
loaded with two 16 bit parallel words, outputs the data as a
32 bit serial word. Timing circuitry inserts a 4 bit gap at the
endofeach32bitword.Aninputbufferregisterallowsload
operations to take place while the previously loaded word
isbeingtransmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity
bit,insertedsoastomakethe32bitwordhaveoddparity.If
the PARITY ENB pin is low, the 32nd bit will be the D15 bit
ofthe2ndwordloaded.
Outputs are provided for both ARINC 429 (TXAOUT and
TXBOUTpins),andARINC561(561DATAand561SYNC
pins)typedata.
A lowsignal appliedtothe
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loadedintothetransmitter.
pin resets the HI-8787’s
TheXMITCLKfrequencyisthesameasthedatarate.
RESET
Input data can be loaded when the XMT RDY signal is
high, which indicates theinput buffer register is empty.The
first 16 bit word is loaded with the A0 input high. The sec-
ondwordisloadedwithA0inthelowstate.Eachdataword
is loaded into the input buffer register by a low pulse on the
input. (See figure 1). After the second word has
been loaded,theXMTRDYoutputgoeslow.Thecontents
oftheinputbufferregisteraretransferredtotheoutputreg-
ister during the fourth bitperiod of the gap. If the fourth gap
bit period of the previous word has already been transmit-
ted, the contents of the input buffer register will be trans-
ferredtotheoutputshiftregisterduringthefirstbitperiodaf-
ter the second data load, and the XMT RDY output goes
high.
After the output shift register is loaded, the data is shifted
outtotheoutputlogicintheordershowninfigure2.
WRITE
The 561 SYNC output pulses low when the XMIT CLK is
low during the 8th bit of the ARINC transmission.
2
HOLT INTEGRATED CIRCUITS
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